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NYU-Processor-Design
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nyu-core
The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
Creative Commons Zero v1.0 Universal
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Task: Outline all modules
#74
ShinyMiraidon
opened
11 months ago
0
Task: Create issues for every connection module
#73
ShinyMiraidon
closed
9 months ago
0
Task: Create issues for every interface
#72
ShinyMiraidon
opened
11 months ago
0
Task: Create issues for every module
#71
ShinyMiraidon
closed
9 months ago
0
Interface: Branch Manager Input
#70
ShinyMiraidon
opened
11 months ago
0
Interface: Data Cache Manager Control
#69
ShinyMiraidon
opened
11 months ago
0
Interface: MEM
#68
ShinyMiraidon
opened
11 months ago
0
Interface: EX
#67
ShinyMiraidon
opened
11 months ago
0
Interface: ID
#66
ShinyMiraidon
opened
11 months ago
0
ignore
#65
ShinyMiraidon
closed
11 months ago
0
Connection Module: Top Level
#64
ShinyMiraidon
opened
11 months ago
2
Ignore
#63
ShinyMiraidon
closed
11 months ago
0
Ignore
#62
ShinyMiraidon
closed
11 months ago
0
Interface: MEM/WB Latch
#61
ShinyMiraidon
closed
11 months ago
0
Interface: EX Stage
#60
ShinyMiraidon
closed
11 months ago
0
Interface: ID Stage
#59
ShinyMiraidon
closed
11 months ago
0
Interface: IF Stage
#58
ShinyMiraidon
closed
11 months ago
0
Ignore
#57
ShinyMiraidon
closed
11 months ago
0
add(component): EX-MEM latch
#56
umanachi
closed
11 months ago
4
docs(Branch-Prediction-Module.md): Added more detail to branch prediction module complex functionality document
#55
ShinyMiraidon
closed
11 months ago
0
add: pc_en enable input
#54
umanachi
closed
11 months ago
2
Add(Branch-Prediction-Module.md): Started Functionality Document for Branch Prediction Module
#53
ShinyMiraidon
closed
11 months ago
0
docs(General Control Module): Added more outputs to I instructions and changes wbs numbers
#52
ShinyMiraidon
closed
11 months ago
0
add: trying to fix register 0
#51
umanachi
closed
11 months ago
2
add: trying to fix register 0
#50
umanachi
closed
11 months ago
0
component(module): Added MEMWB Module and Test
#49
ShinyMiraidon
closed
12 months ago
0
Revert "registers attempt (module + test)"
#48
ShinyMiraidon
closed
1 year ago
0
registers attempt (module + test)
#47
umanachi
closed
1 year ago
1
Registers attempt: module + test
#46
umanachi
closed
1 year ago
0
Updated Module Documentation
#45
ShinyMiraidon
closed
1 year ago
1
Updated and Fixed ALU
#44
ShinyMiraidon
closed
1 year ago
0
docs(core): module doc outlines created and updated
#43
gil92723
closed
1 year ago
1
Core docs
#42
gil92723
closed
1 year ago
0
Made input and output names consistent
#41
ShinyMiraidon
closed
1 year ago
1
Updated Docs
#40
ShinyMiraidon
closed
1 year ago
0
Module: Instruction Cache Manager
#39
ShinyMiraidon
opened
1 year ago
1
IFID Latch Module
#38
ShinyMiraidon
closed
1 year ago
0
docs(cord): 03, 04, 05, 06, doc template created
#37
gil92723
closed
1 year ago
6
docs(core): Updated 00 and 01, Created 02
#36
gil92723
closed
1 year ago
3
docs(core): module functionality - CPU and IF/ID Latch
#35
gil92723
closed
1 year ago
1
docs(core): development & testing process
#34
umanachi
closed
1 year ago
3
program counter: edited test + CMakes
#33
umanachi
closed
1 year ago
1
Documentation: Module Development and Testing Process
#32
ShinyMiraidon
closed
1 year ago
6
program counter: module + test
#31
umanachi
closed
1 year ago
5
Documentation: Module Functionality
#30
ShinyMiraidon
closed
1 year ago
6
Added Branch Evaluation Module and Tests
#29
ShinyMiraidon
closed
1 year ago
1
Moved extension module to cancled folder
#28
ShinyMiraidon
closed
1 year ago
0
Module: Branch Manager
#27
ShinyMiraidon
opened
1 year ago
0
Module: Branch Address Calculator
#26
ShinyMiraidon
opened
1 year ago
0
Module: Branch Predictor
#25
ShinyMiraidon
opened
1 year ago
1
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