issues
search
NYU-Processor-Design
/
nyu-core
The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.
Creative Commons Zero v1.0 Universal
2
stars
12
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Connection Module: MEM
#124
ShinyMiraidon
opened
8 months ago
1
Connection Module: EX
#123
ShinyMiraidon
opened
8 months ago
0
Connection Module: ID
#122
ShinyMiraidon
opened
8 months ago
0
Connection Module: IF
#121
ShinyMiraidon
opened
8 months ago
2
interfaces(MEM.sv, DCache_Manager_Control.sv, Branch_Manager_Input.sv, Alu_Ops.sv, DReg_Info.sv, SReg_Nums.sv): Added Various Interfaces
#120
ShinyMiraidon
closed
8 months ago
0
add(ID.sv) Added ID Interface
#119
ShinyMiraidon
closed
8 months ago
0
docs(01_General_Control_Module.md, 05_General_Control_Module.md): Finished functionality documentation and outline for General Control Module
#118
ShinyMiraidon
closed
8 months ago
0
add(Pipeline_Reset.sv, pipeline_reset.cpp): Added Pipeline Reset Module and Tests
#117
ShinyMiraidon
closed
8 months ago
0
add(Branch_Manager.sv, branch_manager.cpp): Added Branch Manager Module and Tests
#116
ShinyMiraidon
closed
8 months ago
0
docs(10, 03_L1_Data_Cache.md): Updated Documentation
#115
suriyasaiyan
closed
8 months ago
3
docs(01_General_Control_Module.md): Made system instructions nops
#114
ShinyMiraidon
closed
8 months ago
0
Task: Figure out how Environmental Calls and Breakpoints will work
#113
ShinyMiraidon
closed
8 months ago
1
add(branch_manager.cpp, Branch_Manager.sv): Added module and test for branch manager
#112
ShinyMiraidon
closed
8 months ago
3
add(Branch_Predictor.sv, branch_predictor.cpp)
#111
ShinyMiraidon
closed
8 months ago
0
add(idex.cpp, IDEX.sv): Added ID/EX Latch Module implementation and test
#110
ShinyMiraidon
closed
8 months ago
0
update L1_data_cache.md, .sv
#109
suriyasaiyan
closed
8 months ago
2
docs(Branch Prediction): Finalized Branch Prediction Functionality and Finished Branch Prediction outline
#108
ShinyMiraidon
closed
8 months ago
1
Add Branch Address Calculator
#107
gil92723
closed
8 months ago
3
Branch Address Calculator
#106
gil92723
closed
8 months ago
0
Add Branch Address Calculator Modules (To be tested)
#105
gil92723
closed
8 months ago
0
docs(10_Flush_Bus.md): Finished Flush Bus Outline
#104
ShinyMiraidon
closed
9 months ago
0
Interface: Flush Bus
#103
ShinyMiraidon
opened
9 months ago
0
Module: CSR Counters and Registers
#102
ShinyMiraidon
closed
8 months ago
2
docs(interface outlines): Completed various interface outlines
#101
ShinyMiraidon
closed
9 months ago
0
Documentation: The Wiki along with the Dev and Test Guidelines need to be updated to add Interfaces and Connection Modules
#100
ShinyMiraidon
closed
3 months ago
0
docs(01_General-Control-Module.md): Updated General Control Module Outline
#99
ShinyMiraidon
closed
9 months ago
0
add(08_Pipeline_Reset_Module.md): Added Pipeline Reset Module Outline
#98
ShinyMiraidon
closed
9 months ago
0
Task: Figure out cache clock timing
#97
ShinyMiraidon
opened
9 months ago
1
Documentation: Broken links throughout the repo
#96
ShinyMiraidon
closed
9 months ago
1
Connection Module: Data Cache
#95
ShinyMiraidon
opened
9 months ago
1
Connection Module: Instruction Cache
#94
ShinyMiraidon
opened
9 months ago
1
Interface: Instruction Cache Bus
#93
ShinyMiraidon
opened
9 months ago
0
Interface: Source Register Data
#92
ShinyMiraidon
opened
9 months ago
0
Interface: Source Register Numbers
#91
ShinyMiraidon
opened
9 months ago
0
Interface: Destination Register Info
#90
ShinyMiraidon
opened
9 months ago
0
docs(Documentation Folders): Renamed Folders
#89
ShinyMiraidon
closed
9 months ago
0
Interface: ALU Operands
#88
ShinyMiraidon
opened
9 months ago
0
add(02_MEM_Interface.md): Added MEM Interface Outline
#87
ShinyMiraidon
closed
9 months ago
0
docs(Complex-Module-Functions): Updated General Control Module Docs
#86
ShinyMiraidon
closed
9 months ago
0
docs(interface): create EX interface outline
#85
umanachi
closed
9 months ago
2
docs(interface docs): Added ID Interface outline
#84
ShinyMiraidon
closed
9 months ago
0
Task: Finalize Control Signals and Instruction Decoding
#83
ShinyMiraidon
closed
8 months ago
1
Task: Finalize Branch Prediction
#82
ShinyMiraidon
closed
8 months ago
1
Task: Finalize Hazard Detection
#81
ShinyMiraidon
closed
8 months ago
0
Task: Implement all connection modules
#80
ShinyMiraidon
opened
9 months ago
0
Task: Implement all interfaces
#79
ShinyMiraidon
opened
9 months ago
0
Task: Implement all modules
#78
ShinyMiraidon
opened
9 months ago
0
Task: Finalize Cache Designs
#77
ShinyMiraidon
opened
9 months ago
0
Task: Outline all connection modules
#76
ShinyMiraidon
opened
9 months ago
0
Task: Outline all interfaces
#75
ShinyMiraidon
opened
9 months ago
0
Previous
Next