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PyFPGA
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pyfpga
A Python package to use FPGA development tools programmatically.
https://pyfpga.github.io/pyfpga/
GNU General Public License v3.0
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CI: add to verify on Windows
#55
rodrigomelo9
closed
4 weeks ago
0
Implements options
#54
rodrigomelo9
opened
1 month ago
0
Openflow vhdl
#53
rodrigomelo9
closed
1 month ago
0
Re-implement yosys-ise.py and yosys-vivado.py
#52
rodrigomelo9
opened
1 month ago
0
Re-add support for VHDL on Openflow
#51
rodrigomelo9
closed
1 month ago
1
diamond: Use the project name as prefix for the combined constraints
#50
m42uko
closed
1 month ago
1
Bug: Missing configuration of Diamond constraints file
#49
gts-bzi
closed
1 month ago
1
Print actual data when adding configurations to a project
#48
gts-bzi
closed
1 month ago
5
Add support for OPTIONS
#47
rodrigomelo9
opened
1 month ago
0
Feature request: Make loglevel configurable
#46
gts-bzi
closed
1 month ago
3
Feature request: Set TCL filename to project name
#45
gts-bzi
closed
1 month ago
2
Feature request: Make vendor tool path configurable
#44
gts-bzi
closed
1 month ago
2
Implement support for Lattice Diamond
#43
m42uko
closed
1 month ago
18
Feature request: Option to set VHDL version
#42
gts-bzi
opened
3 months ago
1
File paths in TCL on Windows
#41
gts-bzi
closed
2 months ago
3
Constraints classification
#40
gts-bzi
closed
2 months ago
1
Add a Vivado example to run elaboration
#39
rodrigomelo9
closed
1 month ago
1
Add example of a Libero project file to use with prj2bit
#38
rodrigomelo9
closed
2 months ago
1
Add a Vivado example to deal with block designs using hooks
#37
rodrigomelo9
opened
3 months ago
0
Dev
#36
rodrigomelo9
opened
4 months ago
0
I think there is missing 'reset_run impl_1' for Vivado
#35
rodrigomelo9
closed
4 months ago
1
fix: ModuleNotFoundError: No module named 'fpga.helpers'
#34
lmcapacho
closed
1 year ago
1
Rewrite
#33
rodrigomelo9
closed
4 months ago
0
Rewrite - Project
#32
rodrigomelo9
closed
4 months ago
1
Examples to be added
#31
rodrigomelo9
closed
3 months ago
0
Lattice support
#30
rodrigomelo9
closed
4 months ago
1
Prepared for release 0.2.0
#29
rodrigomelo9
closed
2 years ago
0
Add nexys example
#28
rodrigomelo9
closed
2 years ago
0
Fix pylint new complains
#27
rodrigomelo9
closed
2 years ago
0
Add support for openFPGALoader
#26
rodrigomelo9
closed
2 years ago
0
Load FPGA remote
#25
qarlosalberto
closed
2 years ago
4
Doc the current helpers
#24
rodrigomelo9
closed
2 years ago
1
Add vhdl2verilog based on ghdl-yosys-plugn and yosys
#23
rodrigomelo9
closed
4 months ago
1
Add a Libero-SoC project file to use with prj2bit
#22
rodrigomelo9
closed
2 years ago
0
Create a graphical wizard to generate a new project
#21
rodrigomelo9
closed
4 months ago
1
Fix Tcl paths for windows
#20
rodrigomelo9
closed
3 years ago
0
fix path error on windows
#19
motty-mio2
closed
3 years ago
1
Support table
#18
rodrigomelo9
closed
3 years ago
0
ci: fixed 'API reference' generation
#17
rodrigomelo9
closed
3 years ago
0
Add support for more FOSS programmers
#16
rodrigomelo9
closed
4 months ago
3
Improve .pyfpga.yml handling and add an env var to disable docker
#15
rodrigomelo9
closed
2 years ago
1
Improve the Vivado block design example
#14
rodrigomelo9
closed
2 years ago
0
Improve/update the docs
#13
rodrigomelo9
closed
2 years ago
1
Gives a try to pathlib as replace of os.path?
#12
rodrigomelo9
closed
2 years ago
1
Add support for SymbiFlow
#11
rodrigomelo9
closed
2 years ago
1
Add set_arch for VHDL
#10
rodrigomelo9
closed
2 years ago
1
Add set_define for Verilog
#9
rodrigomelo9
closed
2 years ago
1
Verify set_param (type vs tool)
#8
rodrigomelo9
closed
2 years ago
1
Add support for Lattice iCEcube2
#7
rodrigomelo9
closed
2 years ago
0
Add support for Lattice Radiant
#6
rodrigomelo9
closed
2 years ago
0
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