RTimothyEdwards netgen issues

RTimothyEdwards / netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

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issues

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Can't change column width in lvs report

#38 d-m-bailey closed 2 years ago
3
Cosmetic report changes.

#37 d-m-bailey closed 2 years ago
2
Mismatched instance flattening change.

#36 d-m-bailey closed 3 years ago
4
segfaults when running device level LVS on caravel's `chip_io` block with these changes.

#35 d-m-bailey closed 2 years ago
8
Non symmetric processing

#34 d-m-bailey closed 2 years ago
3
Remove disconnected ports after flattening. Recursively flatten unmatched cells with no matching devices. (updated)

#33 d-m-bailey closed 3 years ago
3
Added MacOS (Big Sur) installation instructions.

#32 hpretl closed 3 years ago
1
Add missing newlines to log file messages.

#31 d-m-bailey closed 3 years ago
1
Adding CI to Magic via Vezzal tool

#30 ghost closed 3 years ago
1
Unconnected unmatched ports cause mismatch. Unmatched subckts only partially flattened.

#29 d-m-bailey opened 3 years ago
1
Latest netgen tool hanging

#28 dineshannayya opened 3 years ago
5
Adding CI to Netgen via Vezzal

#27 ghost closed 3 years ago
1
Added command line options -help and -version

#26 mooredan opened 3 years ago
0
If the setup file is present and will be read,

#25 mooredan opened 3 years ago
0
If a setup file is used, warn the user if the netgen

#24 mooredan opened 3 years ago
0
segfault with caravel/chip_io and flattened primitives (example cells) in magic.

#23 d-m-bailey closed 1 year ago
2
Parallel FETs not being merged when drain/source connections are swapped

#22 mooredan opened 3 years ago
5
Disconnected pin not matching between two circuits

#21 donn closed 3 years ago
5
Tool is Wrongly mapping same module two time.

#20 dineshannayya opened 3 years ago
5
Verilog bus map to spice subcircuits in reversed order

#19 d-m-bailey opened 3 years ago
5
Remove netgen.{sh,tcl} and add them to .gitignore

#18 ax3ghazy closed 3 years ago
1
Netgen isn't case sensitive

#17 Manarabdelaty opened 3 years ago
4
Netgen runs out of memory when power connections are missing?

#16 ax3ghazy opened 3 years ago
1
Fix missing prototype for ReadVerilogFile function

#15 just22 closed 3 years ago
1
Increase OBJHASHSIZE

#14 antonblanchard closed 3 years ago
4
Make sure pins from verilog are grouped together in netlist structure

#13 d-m-bailey closed 3 years ago
3
Verilog port processing may be incomplete.

#12 d-m-bailey closed 3 years ago
1
Rework top level ./configure script

#11 mithro closed 3 years ago
2
./configure --with-x doesn't fail if X is not found

#10 mithro opened 3 years ago
0
Why is x11 required for tcl support?

#9 mithro closed 1 year ago
9
netgen doesn't appear to have standard --help or --version?

#8 mithro opened 3 years ago
7
lvs issue with openlane

#7 mattvenn opened 3 years ago
7
Parallel series mosfet matching depends on order of devices

#6 d-m-bailey opened 4 years ago
1
Segmentation fault following symmetry breaking optimization

#5 smunaut closed 6 months ago
1
install fails: cp: netgen: No such file or directory

#4 yurivict closed 4 years ago
9
[1.6.3] warning: multiple unsequenced modifications to 'ActelIndex'

#3 yurivict opened 4 years ago
2
[OpenBSD/ld.bfd] (netgen|magic)exec wants GR_LIBS to link successfully

#2 julianaito closed 4 years ago
3
Got to build on FreeBSD

#1 ghost closed 5 years ago
1