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Reservoir-In-Processor
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rip-sim
Cycle-level simulator for "Reservoir in Processor"
Apache License 2.0
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add two-bit branch predictor (Bimodal predictor)
#84
hirayamy
closed
1 year ago
1
Implement branch history table
#83
hirayamy
closed
1 year ago
0
[RIPSim & Sim] check dhrystone is correctly finished
#82
khei4
closed
12 months ago
1
Unify: Memory and make DRAMSize and DRAMBase variables
#81
khei4
closed
1 year ago
0
[RIPSim] dhry runnable configuration
#80
khei4
closed
1 year ago
0
[RIPSim] calculate memory size requirements for dhry
#79
khei4
closed
1 year ago
1
[BranchPred] Implementation of branch destination buffer
#78
hirayamy
opened
1 year ago
0
[RIPSim]add statistics struct and implement branch distances/instructions count calculation
#77
khei4
closed
1 year ago
0
[RIPSim] rip-sim command option to branch predictor, dump stats, size of DRAM, initial value of sp.
#76
khei4
closed
11 months ago
3
[RIPSim] calculate program stats
#75
hirayamy
closed
1 year ago
2
[Sim] Stats for CPI
#74
hirayamy
closed
1 year ago
1
[RIPSim] 2bit Branch predictor
#73
hirayamy
closed
1 year ago
1
shorten space of register dumps
#72
hirayamy
closed
1 year ago
0
WIP: PoC simplify mret/ecall
#71
khei4
closed
1 year ago
0
PoC: define and use DEBUG_ONLY MACRO for debug only dump
#70
khei4
closed
1 year ago
0
[Sim & RIPSim] variable DRAM size
#69
khei4
closed
1 year ago
1
[RIPSim] Memory implementation separation from Simulator
#68
khei4
closed
1 year ago
2
add verified get methods and fix forwarding
#67
khei4
closed
1 year ago
0
[Sim] implement proceedNInsts and refactor riscv-tests
#66
khei4
opened
1 year ago
0
[RIPSim] testing on stalling
#65
khei4
opened
1 year ago
0
[RIPSim] The timing of modifying PC
#64
hirayamy
closed
1 year ago
0
[RIPSimulator] verify forwarding by defining verified getter for fields
#63
khei4
closed
1 year ago
0
[RIPSim] more precise dump on Forwarding
#62
khei4
closed
11 months ago
1
[RIPSim] clean: CSRdump
#61
khei4
opened
1 year ago
3
Run riscv-tests on RIPSimulator
#60
khei4
closed
1 year ago
0
create: stage level forwarding test
#59
khei4
closed
1 year ago
0
fix forwarding and implement stall for load
#58
khei4
closed
1 year ago
0
WIP: Run: riscv-tests on pipeline simulator
#57
khei4
closed
1 year ago
1
[RIPSim] divide mret status accesses nicely
#56
khei4
opened
1 year ago
0
implement Exception handling, mret and ecall/ebreak on RipSimulator
#55
khei4
closed
1 year ago
0
fix priority between EX and MA and simplify forwarding if
#54
khei4
closed
1 year ago
1
Add naive branch predictor and add stats dump.
#53
hirayamy
closed
1 year ago
8
[RIPSim] stall after load
#52
khei4
closed
1 year ago
0
fix: U-type decoding, and add tests for value equivalence
#51
khei4
closed
1 year ago
0
[RIPSim] Implement Branch Predictor
#50
khei4
closed
1 year ago
1
[RIPSimulator] implement mret, ecall and exceptions
#49
hirayamy
closed
1 year ago
1
[Simulator] No tests for csrrc, csrrsi, and csrrci instructions
#48
hirayamy
opened
1 year ago
1
Add CSR instructions.
#47
hirayamy
closed
1 year ago
1
[RIPSim] pass riscv-tests and dhrystone
#46
hirayamy
closed
1 year ago
0
[Decoder] Bug in instruction decode
#45
hirayamy
closed
1 year ago
0
[Simulator & RIPSim] separate tests
#44
khei4
closed
1 year ago
1
[Simulator] cycle counter
#43
hirayamy
closed
1 year ago
1
Port Simulator instructions, except CSR related, to Pipeline simulator(RIP-simulator)
#42
hirayamy
closed
1 year ago
2
Notation mismatch
#41
hirayamy
opened
1 year ago
1
run riscv-tests and dhry
#40
khei4
closed
1 year ago
0
decode just in time
#39
khei4
closed
1 year ago
0
[Simlator] handle division by zero, overflow
#38
khei4
closed
1 year ago
1
[Simulator] dump CSR regs
#37
khei4
closed
1 year ago
1
[Simulator] Implement User mode and Supervisor mode
#36
khei4
opened
1 year ago
0
[Simulator] add CommonType header
#35
khei4
closed
1 year ago
1
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