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SonalPinto
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kronos
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
https://sonalpinto.github.io/kronos/#/
Apache License 2.0
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Control-flow hijacking vulnerability: Wrong register data is used
#17
KatCe
opened
1 month ago
0
Information Leakage Vuneratbility - via Memory
#16
Mengyuan410
opened
2 months ago
1
Information Leakage Vulnerability
#15
Mengyuan410
opened
2 months ago
1
[Bug report] Unexpected Behavior When Executing Instructions on Non-existent CSRs
#14
youzi27
opened
6 months ago
0
Execution time depends on a data value passed to an addi instruction
#13
KatCe
opened
9 months ago
0
Unexpected manipulation of mtvec register
#12
KatCe
opened
9 months ago
0
Fix hang when writing a CSR in some microarchitectural conditions
#11
flaviens
opened
1 year ago
0
[Bug report] Kronos overcounts the retired instructions
#10
flaviens
opened
1 year ago
0
[Bug report] Processor does not throw an exception when writing to a non-existent CSR
#9
flaviens
opened
1 year ago
0
Bug report: Reading existent CSRs cause the CPU to hang in some microarchitectural conditions
#8
flaviens
opened
1 year ago
0
[Bug report] Processor hangs shortly after reading a non-existent CSR instead of throwing an exception
#7
flaviens
opened
1 year ago
0
Fix triple hazard
#6
flaviens
opened
1 year ago
2
Bug report: stale register value in case of double write
#5
flaviens
opened
1 year ago
2
Remove checks for reserved fields in decode stage for FENCE.I
#4
flaviens
closed
1 year ago
1
Remove checks for reserved fields in decode stage for FENCE
#3
flaviens
closed
1 year ago
2
Linux support
#2
JOHNTBIJU
opened
2 years ago
1
RTL simulation
#1
kingstone1927
opened
3 years ago
1