TheClams SystemVerilog issues

TheClams / SystemVerilog

SystemVerilog plugin for Sublime Text

Apache License 2.0

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issues

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Newest Most commented Recently updated Oldest Least commented Least recently updated

Unable to recognize brackets

#74 WZ-Tong closed 5 months ago
1
Code alignment feature can lead to code breaks in certain scenarios

#73 rayqqqm closed 5 months ago
2
enumerator not showing hints when hovering

#72 ThePeteTree opened 9 months ago
1
apply color to ifdef expressions

#71 jotego opened 10 months ago
1
Configurable indentation

#70 benfroelich closed 1 year ago
1
Latest package causes cursor lag

#69 cmdennett closed 1 year ago
2
module syntax error

#68 godenfreemans closed 1 year ago
3
Is it possible to disable or change ligature for `<=` in assignment statements?

#67 siddhpant closed 1 year ago
2
Tooltip is not displayed properly in latetest version(?)

#66 DaydreamerPP closed 1 year ago
1
Alignment causes code loss/deletion

#65 roowatt closed 1 year ago
1
Function regex issue

#64 sxu55 opened 1 year ago
2
Alignment support blank/comment lines in the signals declaration area?

#63 ch3ch2sh closed 1 year ago
2
Alignment of logic and wire on input/output ports

#62 code-tangent closed 1 year ago
2
hovering mouse over class name in a file doesn't give the preview

#61 naveen2393 closed 1 year ago
1
encoding problem

#60 rayqqqm closed 1 year ago
4
label for autocompletion

#59 xinpan1992 closed 1 year ago
1
Syntax highlighting inconsistent for port connections of sub module

#58 maxbjurling closed 1 year ago
2
[Highlight] Support size prefix for %t formatting specifications

#57 donlon opened 2 years ago
0
File encode

#56 godenfreemans closed 1 year ago
2
Prioritize auto-completion to reserved keywords

#55 perchrc opened 2 years ago
1
nested if-else constraints highlighting issues

#54 erihsu closed 2 years ago
1
Could you fix this, please?

#53 mrBitman closed 2 years ago
1
How to set a project?

#52 slumpedyeti closed 1 year ago
3
`ifdef `else `if -> how handled?

#51 ldm1417 closed 2 years ago
1
auto completion of module parameter not working for tag 3.1.5 in ST4

#50 PeteTreeUk closed 1 year ago
9
Hint macro define feature

#49 erihsu closed 2 years ago
1
Highlight function being edited in module hierarchy

#48 jbshaler opened 2 years ago
0
Quartus Project -> supporting?

#47 ldm1417 closed 2 years ago
1
Instance Name indication in the Port Declaration

#46 ldm1417 closed 2 years ago
1
How can I include external file for auto-completion with environment variables

#45 erihsu closed 2 years ago
1
packed array bracket shows false syntax error

#44 Ali-Flt closed 2 years ago
1
Lof of CPU usage when I type dot

#43 mickaelgnb closed 2 years ago
9
keyword highlighting issue

#42 erihsu closed 2 years ago
3
Disable end parenthesis alignment?

#41 perchrc closed 3 years ago
1
Navigate to subfield definition in sv

#40 erihsu closed 3 years ago
2
SystemVerilog parser does not recognise scope resolution when using spaces

#39 nils-exibard closed 3 years ago
0
keywords highlighting issues

#38 erihsu closed 3 years ago
1
Several useful features for Verilog / SystemVerilog

#37 Fynjisx26 opened 3 years ago
0
LSP Support?

#36 ghost opened 3 years ago
0
auto completion of module parameter not working for tag 3.0.9 in ST4

#35 PeteTreeUk closed 3 years ago
0
negedge completes to posedge

#34 PGAElger closed 3 years ago
0
Incorrect syntax highlight when using `ifdef `else `endif for module instance in ST4

#33 nils-exibard closed 3 years ago
0
Instance generator doesn't work with package declaration defined in module port list.

#32 mm4dd closed 3 years ago
6
ST4 Support

#31 roowatt closed 3 years ago
2
Union autocomplete doesn't work

#30 LS1222 closed 3 years ago
0
Is it possible to support the completion of verilog and sv's keywords?

#29 maxwell-zhu2021 closed 3 years ago
1
cannot turn off autocomplete

#28 aaleclaire closed 3 years ago
3
Hierarchy viewing is not working if there are multiple classes defined in the same file

#27 DeeeeLAN closed 3 years ago
1
Reindenting typedefs indents poorly

#26 DeeeeLAN opened 3 years ago
3
autocomplete faied

#25 caltech-chen closed 3 years ago
0