UHCL-CENG-SeniorProject-2021 FPGA issues - Githubissues

UHCL-CENG-SeniorProject-2021 / FPGA

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Familiarize with Serial Arguments

#21 marybethg123 opened 3 years ago
0
Initialize audio codec SSM2603

#20 marybethg123 opened 3 years ago
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W/R register map of i2c

#19 marybethg123 opened 3 years ago
0
W/R for i2c device

#18 marybethg123 opened 3 years ago
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updated build.tcl to include i2c files

#17 bklolo closed 3 years ago
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UART/SPI/I2C merge

#16 bklolo closed 3 years ago
0
Create i2s_ctrl component

#15 bklolo opened 3 years ago
1
path.bash made more generic

#14 bklolo closed 3 years ago
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path in path.bash more generic, added comment to ahbuart_test.py

#13 bklolo closed 3 years ago
1
Sim test

#12 bklolo closed 3 years ago
0
Test

#11 bklolo closed 3 years ago
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sim.bash has unnecessary code

#10 bklolo closed 3 years ago
1
Test

#9 bklolo closed 3 years ago
0
Test -> Master

#8 bklolo closed 3 years ago
0
Setup simTest Branch for cocotb

#7 UHCL-CENG-SeniorProject-2021 closed 3 years ago
1
grlib_tester / logic_top

#6 bklolo closed 3 years ago
2
zybo_top / test_top integration

#5 bklolo closed 3 years ago
1
cleaned up a little, still debugging

#4 UHCL-CENG-SeniorProject-2021 closed 3 years ago
0
test_issue

#3 bklolo closed 3 years ago
2
Test Conflict

#2 marybethg123 closed 3 years ago
0
Branch Test

#1 marybethg123 closed 3 years ago
0