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amaranth-lang
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amaranth-soc
System on Chip toolkit for Amaranth HDL
BSD 2-Clause "Simplified" License
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csr.bus: replace ceil(log2(n)) with log2_int(n, need_pow2=False).
#50
jfng
closed
1 year ago
0
Migrate bus primitives to `amaranth.lib.wiring`
#49
jfng
closed
1 year ago
7
wishbone.bus: migrate to lib.wiring interfaces.
#48
jfng
closed
1 year ago
1
wishbone.bus: remove deprecated use of Repl.
#47
jfng
closed
1 year ago
0
pyproject: synchronize with Amaranth
#46
whitequark
closed
1 year ago
0
Updates for Python 3.8+
#45
whitequark
closed
1 year ago
0
Update .gitignore
#44
whitequark
closed
1 year ago
0
Add CODEOWNERS
#43
whitequark
closed
1 year ago
0
csr.bus: fix typos.
#42
jfng
closed
1 year ago
0
csr.bus: redesign Multiplexer shadow registers.
#41
jfng
closed
1 year ago
3
Implement RFC 16 (CSR register API)
#40
jfng
closed
7 months ago
3
Resources on dense memory windows must be sized multiples of "parent" data_width?
#39
chenz
opened
1 year ago
0
Should wishbone.Decoder generate bus errors for unmapped addresses?
#38
chenz
opened
1 year ago
5
[pre?-RFC] Generic constant-frequency enable generator
#37
galibert
opened
1 year ago
4
Constructing Wishbone interface with a single memory window is overly complex / uses redundant parameters
#36
galibert
opened
1 year ago
12
wishbone: fix docstring typo.
#35
jfng
closed
1 year ago
0
[pre-RFC] Ideas for an I2C peripheral interface on Wishbone
#34
galibert
opened
1 year ago
2
PyPi package is empty
#33
hansfbaier
opened
2 years ago
1
csr.wishbone: Only ack for 1 cycle
#32
antonblanchard
closed
3 years ago
3
wishbone.bus.Decoder: Only assert stb when slave is selected
#31
antonblanchard
opened
3 years ago
2
csr/bus: Take data width into account for register writes
#30
kbeckmann
opened
3 years ago
0
SRAM bus
#29
Fatsie
opened
3 years ago
0
CSR: Export Wishbone bridge from nmigen_soc.csr
#28
Fatsie
opened
3 years ago
0
Provide a naming mechanism for memory map resources and windows
#27
jfng
closed
2 years ago
0
Make optional properties return None while uninitialized.
#26
jfng
opened
4 years ago
1
periph: add a ConstantMap container for configuration constants.
#25
jfng
closed
4 years ago
1
Communicating constants from the peripheral to the BSP generator
#24
jfng
closed
4 years ago
0
test: make nmigen 0.3+ compatible
#23
rroohhh
closed
4 years ago
4
Use 0 as default for lock on subordinate bus
#22
Fatsie
closed
4 years ago
2
[WIP]wishbone.Connector class
#21
Fatsie
opened
4 years ago
5
Handling resource name collisions inside a MemoryMap
#20
jfng
closed
2 years ago
1
periph: add a PeripheralInfo class for metadata.
#19
jfng
closed
4 years ago
3
Wishbone access from initiator bus with data_width smaller than the one of the subordinate bus.
#18
Fatsie
opened
4 years ago
9
Test positional and keyword argument passing
#17
Fatsie
closed
4 years ago
2
csr.event: add event monitor.
#16
jfng
closed
4 years ago
2
more fine-grained memorymap
#15
anuejn
closed
4 years ago
2
wishbone.bus: fix Decoder case pattern.
#14
jfng
closed
4 years ago
3
csr.wishbone: fix WishboneCSRBridge cycle counter.
#13
jfng
closed
4 years ago
3
Add event management primitives
#12
jfng
closed
4 years ago
4
csr.periph: add Peripheral base class.
#11
jfng
opened
4 years ago
5
Peripheral API design: exposing bus interfaces
#10
jfng
opened
4 years ago
7
wishbone.bus: add Arbiter.
#9
jfng
closed
4 years ago
2
setup: require nmigen>=0.1,<0.3.
#8
emilazy
closed
4 years ago
2
Add support for extending the address space of a memory map
#7
jfng
closed
4 years ago
4
Clarify documentation for alignment parameters to mention that it is log2
#6
jfng
closed
4 years ago
7
csr.bus.Element: fix src_loc_at.
#5
nmigen-issue-migration
closed
4 years ago
2
SyntaxError when wishbone.Decoder data width is equal to granularity
#4
nmigen-issue-migration
closed
4 years ago
0
wishbone.bus: add Arbiter.
#3
nmigen-issue-migration
closed
4 years ago
3
[Request] A proposal for CSRs
#2
nmigen-issue-migration
closed
3 months ago
4
Control/status registers
#1
nmigen-issue-migration
closed
3 months ago
16
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