armleo ArmleoCPU issues

armleo / ArmleoCPU

ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set

GNU General Public License v3.0

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issues

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axi_bram has fixed width because of 1rwm address logic

#78 armleo opened 3 years ago
0
RISC-V Timer can be optimized

#77 armleo opened 3 years ago
0
AXI4 Router needs more tests

#76 armleo closed 2 years ago
1
Remove response stage from Cache. Let it be responsibility of the pipeline itself. This solution is more optimal.

#75 armleo closed 3 years ago
1
Exclusive monitor implementation is wrong. More optimal solution is possible.

#74 armleo opened 3 years ago
4
Cache: REQ READY undriven

#73 armleo closed 3 years ago
1
Add more tests testing limits of TLB (including victim_way checking)

#72 armleo opened 3 years ago
0
Implement CSR remaining commands

#71 armleo opened 3 years ago
0
Fix Cache implementation

#70 armleo opened 3 years ago
1
Verilator Lints: Remove global lint off-s

#69 armleo opened 3 years ago
0
Interrupt after branch taken contains incorrect PC

#68 armleo opened 3 years ago
0
QSPI Flash and QSPI PSRAM controller

#67 armleo closed 2 years ago
1
Skywater130 tapeout

#66 armleo opened 3 years ago
0
New Pipelined Cache architecture with 3 cycle deep pipeline

#65 armleo opened 3 years ago
1
Fetch: stress test using verilator

#64 armleo closed 3 years ago
0
Fetch: New branch taken implementation with pending active Cache request canceling

#63 armleo closed 3 years ago
1
AXI Register Slice

#62 armleo opened 3 years ago
0
Fix image docker versions

#61 armleo closed 3 years ago
1
More CSR Tests

#60 armleo opened 3 years ago
0
Make CLINT/PLIC CXXRTL models and run them under qemu or spike

#59 armleo opened 3 years ago
1
More Cache tests

#58 armleo opened 3 years ago
0
Cache: Test case Read after write should be stalled for one cycle at least

#57 armleo closed 3 years ago
1
BUG: continious load-reserves on one core and amo rmw operations on another one causes perfomance degradation

#56 armleo closed 3 years ago
1
Some peripherals don't properly return IDs, test this properly because b_expect does not check id value

#55 armleo opened 3 years ago
0
Change branch names to make 0.0.2 as main/default branch, and add information in Readme about branches

#54 armleo closed 3 years ago
0
Implement ATOMIC Read-Modify-Write Instructions

#53 armleo opened 3 years ago
0
Implement simple UART8250

#52 armleo opened 3 years ago
0
Implement CLINT/PLIC

#51 armleo opened 3 years ago
4
Cache: Write should not invalidate cache data, instead just write it to storage

#50 armleo opened 3 years ago
0
Add LICENSE file and add mention of this file in headers of all files

#49 armleo closed 3 years ago
0
Generic yosys synthesis makefile

#48 armleo closed 3 years ago
1
Add formal verification

#47 armleo opened 3 years ago
9
AXI Arbiter

#46 armleo opened 3 years ago
0
New Cache architecture

#45 armleo closed 3 years ago
2
chip2chip

#44 armleo opened 3 years ago
0
AXI4 Router

#43 armleo closed 3 years ago
1
Copyright notices

#42 armleo closed 3 years ago
2
Add armleocpu_undef.vh.

#41 armleo closed 3 years ago
2
Proper verif-isa-tests environment

#40 armleo opened 3 years ago
0
AXI_BRAM: Proper assertions/debug statements

#39 armleo closed 3 years ago
1
Fix tests

#38 armleo closed 3 years ago
5
Pagefault for atomic requests not handled

#37 armleo closed 3 years ago
1
Default nettype wire

#36 armleo closed 3 years ago
1
Cache size reduction

#35 armleo closed 3 years ago
1
Simpler memory

#34 armleo closed 3 years ago
1
Future: bus between cores

#33 armleo closed 3 years ago
1
New Decode + Pipeline

#32 armleo opened 3 years ago
0
New Fetch

#31 armleo closed 3 years ago
3
Write through buffer

#30 armleo opened 3 years ago
0
PTW AXI4

#29 armleo closed 3 years ago
1