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image::blarney-logo.svg#gh-light-mode-only[Blarney logo, width=275] image::blarney-logo-dark.svg#gh-dark-mode-only[Blarney logo, width=275]
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Blarney is a Haskell library for hardware description that builds a range of HDL abstractions on top of a small set of pure functional circuit primitives. It is a modern variant of http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.110.5587&rep=rep1&type=pdf[Lava] using many of the latest features of GHC. Some aspects of the library are also inspired by https://github.com/B-Lang-org/bsc[Bluespec], such as first-class actions and method-based interfaces.
== Prerequisites
We'll need Verilator and GHC 9.2.1 or later.
On Ubuntu 20.04, we can do:
For GHC 9.2.1 or later, https://www.haskell.org/ghcup/[ghcup] can be used.
== Quick start
To clone the repo:
To simulate the https://github.com/blarney-lang/blarney/tree/master/Examples/Sorter/Sorter.hs[Sorter] example from Blarney's https://github.com/blarney-lang/blarney/tree/master/Examples[Examples] directory:
You should see the output:
To run the regression test suite:
To start development of your own Blarney application or library, take a look at the https://github.com/blarney-lang/template-project/[Blarney template project].
== Documentation
See https://github.com/blarney-lang/blarney/blob/master/Doc/ByExample.adoc[Blarney by Example], our introduction to Blarney, which supplements the http://blarney-lang.github.io/blarney/index.html[Haddock docs].
== Applications
Our current list of applications developed using Blarney:
https://github.com/blarney-lang/actora/[Actora]: A 3-stage stack processor that runs code written a subset of Erlang. It has higher performance density than Intel's register-based NIOS-II core for compiled Erlang code.
https://github.com/CTSRD-CHERI/SIMTight/[SIMTight]: A https://cheri-cpu.org[CHERI]-enabled RISC-V GPGPU with dynamic scalarisation features and high performance density on Intel's Stratix 10 FPGA.
https://github.com/blarney-lang/five/[Five]: A formally verified implementation of the classic 5-stage RISC pipeline as an abstract component, largely independent of any specific instruction set.
https://github.com/blarney-lang/five-alive/[FiveAlive]: A proof-of-concept instantiation of the https://github.com/blarney-lang/five/[Five] pipeline with the RISC-V instruction set to give a simple 32-bit microcontroller.