issues
search
chipsalliance
/
f4pga-v2x
Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
https://f4pga-v2x.readthedocs.io/en/latest/
Apache License 2.0
10
stars
12
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
v2x module tests
#18
glatosinski
closed
4 years ago
2
V2X cannot handle directly assigned wires
#17
kgugala
opened
4 years ago
1
Added __init__.py to v2x/xml
#16
glatosinski
closed
4 years ago
1
Add entry points for the tools
#15
mithro
opened
4 years ago
0
Set up Conda for installing tools needed in tests
#14
kgugala
opened
4 years ago
1
Add CI and format the code so it passes flake8 test
#13
kgugala
closed
4 years ago
0
docs: Adding some initial documentation.
#12
mithro
closed
4 years ago
1
Figure out how to run the v2x tests
#11
mithro
opened
4 years ago
0
Import history from symbiflow-arch-defs repository
#10
mithro
closed
4 years ago
0
Import timing from SDF files
#9
mithro
opened
4 years ago
0
Use Yosys Python binding rather than running Yosys
#8
mithro
opened
4 years ago
0
Pull in some history from arch-defs repository
#7
mithro
opened
4 years ago
0
return strings from the module functions
#6
kgugala
closed
4 years ago
0
Update the README file
#5
mithro
opened
4 years ago
0
Create documentation
#4
kgugala
opened
4 years ago
2
Build yosys during installation
#3
kgugala
closed
4 years ago
3
Move yosys python wrapper to a separate repo?
#2
kgugala
opened
4 years ago
3
Set up CI
#1
kgugala
closed
4 years ago
0
Add support for loading timing information in v2x from SDF
#35
mithro
opened
5 years ago
4
Previous