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chipsalliance
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f4pga-v2x
Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
https://f4pga-v2x.readthedocs.io/en/latest/
Apache License 2.0
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docs: Use no-license directive
#69
daniellimws
closed
4 years ago
1
Publish to PyPi
#68
mithro
opened
4 years ago
0
muxes/use_mux.sim.v test
#67
mithro
opened
4 years ago
0
Install tox inside the conda environment.
#66
mithro
closed
4 years ago
0
Port to using conda-env-make
#65
mithro
opened
4 years ago
3
Make V2X use Surelog instead of Yosys
#64
mkurc-ant
opened
4 years ago
1
docs: Change to use symbiflow's theme
#63
daniellimws
closed
4 years ago
0
Make sure "SymbiFlow Parts Encyclopedia" is updated
#62
mithro
opened
4 years ago
0
Document the `(* whitebox *)` (and related attribute)
#61
mithro
opened
4 years ago
2
ci: Add scripts to check for necessary headers
#60
daniellimws
closed
4 years ago
3
Add license headers to setup.py and docs/conf.py
#59
daniellimws
closed
4 years ago
0
Pin verilog-diagram to an older version to stop build from failing
#58
daniellimws
closed
4 years ago
0
Include README in the docs
#57
daniellimws
closed
4 years ago
0
Add setup.py entry point to install v2x binary
#56
daniellimws
closed
4 years ago
2
Make sure info in @kgugala's talk is in the v2x documentation
#55
mithro
opened
4 years ago
0
Make sure the contents of the top level `README.md` appear in the readthedocs output
#54
mithro
closed
4 years ago
2
Make sure that a `v2x` binary is installed using setup.py's script entry points
#53
mithro
closed
4 years ago
0
Add verible's Verilog auto-formatter to the repository
#52
mithro
opened
4 years ago
0
Add a `make format` and `make format-check` to the repository for the python code
#51
mithro
opened
4 years ago
0
Come up with a good "template" for documentation of the tests
#50
mithro
opened
4 years ago
4
Add symbolator rendered module blocks to the documentation
#49
mithro
opened
4 years ago
0
Figure out how to use netlistsvg with single whitebox modules
#48
mithro
opened
4 years ago
1
Figure out how to skip copyright header in verilog output in rendered Sphinx docs
#47
mithro
closed
4 years ago
5
Add basic information to README
#46
daniellimws
closed
4 years ago
1
Add the readthedocs dependencies to environment.yml
#45
mithro
closed
4 years ago
0
Require latest version of sphinx.
#44
mithro
closed
4 years ago
0
readthedocs run fails with "TypeError: connect() got an unexpected keyword argument 'priority'"
#43
mithro
closed
4 years ago
3
Update documentation for clock examples
#42
daniellimws
closed
4 years ago
20
Allow docs/Makefile to be portable
#41
daniellimws
closed
4 years ago
3
Missing golden.pb_type.xml in some test cases
#40
daniellimws
opened
4 years ago
4
Add license header to top of all code files
#39
daniellimws
closed
4 years ago
7
Add license header to top of all code files
#38
mithro
closed
4 years ago
1
Adding .gitattributes for GitHub language detection.
#37
mithro
closed
4 years ago
1
Explicit combinational sink list
#36
mkurc-ant
closed
4 years ago
8
Enchance clock detection
#34
mkurc-ant
closed
4 years ago
0
Improved Yosys error handling
#33
mkurc-ant
closed
4 years ago
0
Fasm annotation support
#32
mkurc-ant
opened
4 years ago
20
Fixed dependency specification in setup.py
#31
mkurc-ant
closed
4 years ago
0
Improving the README file a little.
#30
mithro
closed
4 years ago
0
Added support for defining IO cells
#29
mkurc-ant
closed
4 years ago
1
Fixes for interconnect generation
#28
mkurc-ant
closed
4 years ago
0
Added NO_COMB annotation.
#27
mkurc-ant
closed
4 years ago
3
Reworked net attribute retrieval
#26
mkurc-ant
closed
4 years ago
1
Model for DFF with enable input is generated with combinational port relation
#25
mglb
opened
4 years ago
0
Remove exec permission from files not intended for execution
#24
mglb
closed
3 years ago
0
Remove shebangs
#23
mglb
closed
4 years ago
2
Changing outputs of the vlog_to_pbtype function in Python 3.5
#22
glatosinski
opened
4 years ago
3
Error with installing vtr_xml_utils dependency on Travis CI
#21
glatosinski
opened
4 years ago
0
Yosys: do not optimize designs during evaluation
#20
kgugala
closed
3 years ago
3
Handle input and output classes
#19
kgugala
closed
4 years ago
3
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