chipsalliance f4pga-xc-fasm2bels issues

chipsalliance / f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

Apache License 2.0

10 stars 12 forks source link

issues

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RAM32X1S element on A6 LUT not processed correctly

#93 kraemv opened 9 months ago
0
[WIP] [DNM] CI Test

#92 mkurc-ant opened 11 months ago
0
Support for DSP

#91 ad-astra-et-ultra closed 11 months ago
1
Bump yosys and prjxray versions

#90 jgoeders closed 1 year ago
2
prevent using LUT6_2?

#89 zliu1Charlotte opened 1 year ago
1
issue on fasm to Verilog urgent

#88 zliu1Charlotte closed 1 year ago
15
ci: update custom runners labels

#87 AdamOlech closed 1 year ago
0
Changes requested to README

#86 TheDHCreator closed 2 years ago
5
Merging old commits from BYU/fasm2bels fork in light of Apache rebrand

#85 TheDHCreator closed 2 years ago
3
ci: add custom runners usage

#84 acomodi closed 2 years ago
0
Relicense to Apache-2.0

#83 kgugala closed 2 years ago
0
Assertion error with F4PGA-produced .fasm

#82 wkkuna opened 2 years ago
1
Added ALU equialence checking data

#81 Dumbledork01 closed 2 years ago
10
Added Equivalence Checking for alu.v

#80 Dumbledork01 closed 2 years ago
0
about add dsp to fasm2bels

#79 KKtiandao opened 2 years ago
7
f4pga or fpga?

#78 TheDHCreator closed 2 years ago
2
Report all site features when no supported site feature is found

#77 gergoerdi closed 2 years ago
1
Assertion error on Symbiflow-produced `.fasm` file

#76 gergoerdi opened 2 years ago
3
Inconsistent CLI flags

#75 gergoerdi opened 2 years ago
0
Added CI check for environment creation

#74 jaromharris closed 2 years ago
2
Add CI which runs the development environment

#73 mithro opened 2 years ago
5
Fixed broken env target

#72 jaromharris closed 2 years ago
3
env target broken with make-env

#71 jgoeders closed 2 years ago
6
Improve readme

#70 acomodi closed 3 years ago
0
Adding installation instructions for FASM2BELs

#69 TheDHCreator closed 3 years ago
3
Equivalence checking

#68 jaromharris closed 2 years ago
9
license: exclude golden verilog files from check

#67 acomodi closed 3 years ago
0
Unconnected CARRY4s fix

#66 jaromharris closed 3 years ago
6
Added license headers to verilog files

#65 jaromharris closed 3 years ago
5
Add license header to Verilog files

#64 jgoeders opened 3 years ago
2
Handle IOB that provides PUDC functionality

#63 jgoeders closed 3 years ago
15
Xc-fasm2bels is getting error out while running running picoSoC design

#62 dhruvk-umass closed 3 years ago
2
Unconnected CARRY4s

#61 the-centry closed 3 years ago
2
fasm2bels: fix comment to the connection_database argument

#60 acomodi opened 3 years ago
0
Running bug?

#59 the-centry closed 3 years ago
4
Fix licenses

#58 acomodi closed 3 years ago
1
database: add main to create_channels function

#57 acomodi closed 3 years ago
0
Add license checking github action

#56 mithro closed 3 years ago
1
Remove directly rapidyaml reference from requirements.

#55 litghost closed 3 years ago
0
gh-actions: ci: update clang-format and g++ to v8

#54 kowalewskijan closed 3 years ago
2
Unconnected CARRY4s

#53 mbpeterson70 closed 3 years ago
9
BUFHCE route-through handling

#52 mkurc-ant closed 3 years ago
6
models: cmt: add ADV to cmt prefix

#51 acomodi closed 3 years ago
4
Add PCIe primitive model

#50 kowalewskijan closed 3 years ago
0
Add gtp primitives

#49 acomodi closed 3 years ago
1
Extra/unused LUTs in output design

#48 mbpeterson70 closed 3 years ago
1
Update FPGA interchange schema path.

#47 litghost closed 3 years ago
0
Add TODO referencing issue to requirements.txt for RapidYaml.

#46 litghost closed 3 years ago
0
Add rapidyaml to requirements.

#45 litghost closed 3 years ago
0
PLL and MMCM decoding fixes

#44 mkurc-ant closed 3 years ago
9