emu-russia dmgcpu issues

emu-russia / dmgcpu

DMG CPU Reverse Engineering

Creative Commons Zero v1.0 Universal

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issues

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clarified about sense amp

#309 ogamespec closed 2 months ago
0
hram_netlist.png

#308 ogamespec closed 2 months ago
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hram info

#307 ogamespec closed 2 months ago
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hram section

#306 ogamespec closed 2 months ago
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ser done

#305 ogamespec closed 2 months ago
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ser ports

#304 ogamespec closed 2 months ago
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div -> ser

#303 ogamespec closed 2 months ago
0
Update sck_tran.png

#302 ogamespec closed 2 months ago
0
SCK pad

#301 ogamespec closed 2 months ago
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removed pages (always broken)

#300 ogamespec closed 2 months ago
0
Update pads.md

#299 ogamespec closed 2 months ago
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CK1_CK2 tran

#298 ogamespec closed 2 months ago
0
org_to_msinger.py

#297 ogamespec closed 2 months ago
0
clkgen cells map

#296 ogamespec closed 2 months ago
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clkgen netlist

#295 ogamespec closed 2 months ago
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Purpose of the Research

#294 ogamespec closed 2 months ago
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Reference section

#293 ogamespec closed 2 months ago
0
Speed up simulation by ~35 times by using Yosys and Verilator

#292 Rodrigodd closed 2 months ago
1
wave of soc research

#291 ogamespec closed 2 months ago
0
SoC Top-level

#290 ogamespec opened 3 months ago
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Add basic content on SoC research

#289 ogamespec opened 3 months ago
0
Update clk.md

#288 ogamespec closed 4 months ago
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Expanding the repository for SoC research purposes

#287 ogamespec closed 4 months ago
0
Minor edits

#286 ogamespec closed 5 months ago
0
Prepare repository for SoC research results

#285 ogamespec closed 4 months ago
0
Update design

#284 ogamespec closed 7 months ago
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Update design

#283 ogamespec closed 7 months ago
0
Try to fix verilator and tidy up `cpu_instrs` emulation

#282 Rodrigodd closed 7 months ago
2
blargg cpu_instrs test (cpu_instrs.mem)

#281 ogamespec closed 7 months ago
0
Fix `DataMux`

#280 Rodrigodd closed 7 months ago
0
not about ebus/fbus inverter

#279 ogamespec closed 8 months ago
0
conditional jump test rom

#278 ogamespec closed 8 months ago
0
JR opcode

#277 ogamespec closed 7 months ago
7
Use of CLK7

#276 ogamespec closed 8 months ago
0
about overlapped execution

#275 ogamespec closed 8 months ago
0
Check CLK7 usage

#274 ogamespec closed 8 months ago
1
about CLK7

#273 ogamespec closed 8 months ago
0
replaced precharge by z in ALU dynamic random logic

#272 ogamespec closed 8 months ago
0
Transparent latches for asymmetric CLK in ALU random logic

#271 ogamespec closed 8 months ago
0
Investigate branching

#270 Rodrigodd closed 8 months ago
0
Cracked ALU_Out1 signal meaning

#269 ogamespec closed 8 months ago
0
ALU_Out1 = ~cond_ok

#268 ogamespec closed 8 months ago
0
cc_check schematics

#267 ogamespec closed 8 months ago
1
Test the cc check circuit

#266 ogamespec closed 8 months ago
11
roms folder for test bench runs

#265 ogamespec closed 8 months ago
0
Signal rename Maybe1/Maybe2 -> BUS_DISABLE/IPL_DISABLE

#264 ogamespec closed 8 months ago
0
minor HDL edits

#263 ogamespec closed 8 months ago
0
minor wiki fix

#262 ogamespec closed 8 months ago
0
dmg_waves

#261 ogamespec closed 8 months ago
0
Z/W regs active low input and bus polarity clarify

#260 ogamespec closed 8 months ago
0