issues
search
emu-russia
/
dmgcpu
DMG CPU Reverse Engineering
Creative Commons Zero v1.0 Universal
29
stars
4
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
lol typo
#259
ogamespec
closed
8 months ago
0
wiki minor edits
#258
ogamespec
closed
8 months ago
0
fixed bogus hw again lol
#257
ogamespec
closed
8 months ago
0
fixed xx in bogus hw
#256
ogamespec
closed
8 months ago
0
Fighting databus
#255
ogamespec
closed
8 months ago
0
WR hack for data mux
#254
ogamespec
closed
8 months ago
0
fixed external databus floaters
#253
ogamespec
closed
8 months ago
0
updated tests and wiki (decoder3)
#252
ogamespec
closed
8 months ago
0
Fixed decoder3 stupid typo
#251
ogamespec
closed
8 months ago
0
datamux tran
#250
ogamespec
closed
8 months ago
0
Update buses.md
#249
ogamespec
closed
8 months ago
0
Update buses.md
#248
ogamespec
closed
8 months ago
0
Bidirectional bus multiplexing wiki
#247
ogamespec
closed
8 months ago
0
DataMux = DataLatch + DataBridge combined
#246
ogamespec
closed
8 months ago
0
Combine DataLatch+DataBridge into single module - DataMux
#245
ogamespec
closed
8 months ago
0
redone DataLatch for logisim
#244
ogamespec
closed
8 months ago
0
datalatch wiki update
#243
ogamespec
closed
8 months ago
0
Opcode 77 waves
#242
ogamespec
closed
8 months ago
0
Path pics
#241
ogamespec
closed
8 months ago
0
Value of registers are stored inverted.
#240
Rodrigodd
closed
8 months ago
10
CPU never writes to external bus
#239
Rodrigodd
closed
8 months ago
12
Run instructions in the CPU
#238
Rodrigodd
closed
8 months ago
3
Fixed azo8,9 in ALU (typo)
#237
ogamespec
closed
8 months ago
0
Fight with ALU continues
#236
ogamespec
closed
8 months ago
0
ALU clarifications
#235
ogamespec
closed
8 months ago
0
Update ALU.v
#234
ogamespec
closed
8 months ago
0
Fight with ALU
#233
ogamespec
closed
8 months ago
0
found missing DLatch (shifter result)
#232
ogamespec
closed
8 months ago
0
HDL updated
#231
ogamespec
closed
8 months ago
0
Fixed g84 CLK inputs
#230
ogamespec
closed
8 months ago
0
Verify ALU
#229
ogamespec
closed
8 months ago
10
Update external_clk.v
#228
ogamespec
closed
8 months ago
0
Clarified use of CLK9/8 in seq dffs
#227
ogamespec
closed
8 months ago
0
Verify CLK trees
#226
ogamespec
closed
8 months ago
1
CLK2/1 for g84
#225
ogamespec
closed
8 months ago
0
polished seq logisim
#224
ogamespec
closed
8 months ago
0
Update seq_netlist.png
#223
ogamespec
closed
8 months ago
0
fixed module4_2
#222
ogamespec
closed
8 months ago
0
logisim seq png
#221
ogamespec
closed
8 months ago
0
seq logisim wip
#220
ogamespec
closed
8 months ago
0
`CLK_ENA` should only go high after `OSC_STABLE`
#219
Rodrigodd
closed
8 months ago
36
Renamed some externals signals
#218
ogamespec
closed
1 year ago
0
Cleaned up Seq
#217
ogamespec
closed
1 year ago
0
Use GekkioNames
#216
ogamespec
closed
2 years ago
0
Reverted PC to using w/x
#215
ogamespec
closed
2 years ago
0
Use Gekkio names
#214
ogamespec
closed
2 years ago
0
LoadIR port -> M1
#213
ogamespec
closed
2 years ago
0
Update Readme.md
#212
ogamespec
closed
2 years ago
0
Rename LoadIR port -> M1
#211
ogamespec
closed
2 years ago
0
Fixed bq7 typo
#210
ogamespec
closed
2 years ago
0
Previous
Next