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enjoy-digital
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xtrx_julia
XTRX LiteX/LitePCIe based design for Julia Computing
BSD 2-Clause "Simplified" License
24
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Gain distribution
#25
zsoerenm
closed
2 years ago
0
DC Offset and Channel-Specific Settings
#24
sjkelly
closed
2 years ago
0
Small improvements to build system
#23
staticfloat
closed
2 years ago
0
Mb/channelsounding
#22
mbaz
closed
2 years ago
1
Update from https://github.com/JuliaComputing/xtrx_julia.
#21
enjoy-digital
closed
2 years ago
0
gateware/lms7002m: Use rx_frame to align rx_converter/64-bit data.
#20
enjoy-digital
closed
2 years ago
0
gateware/lms7002m: Decouple I/Q on Generator/Checker by using different increments.
#19
enjoy-digital
closed
2 years ago
0
Revert "Sjk/64bitup1"
#18
sjkelly
closed
2 years ago
0
Sjk/64bitup1
#17
sjkelly
closed
2 years ago
1
SIM Interface pins/GPIO
#16
hemanthmab
closed
2 years ago
1
Add a LICENSE file?
#15
mithro
closed
2 years ago
4
Firmware changes for Rev5
#14
sjkelly
closed
2 years ago
0
Confirm critical errors in gateware vivado compiling.
#13
Godtec
opened
2 years ago
2
software/app: Make it CPU/GPU compatible (if GPU support is required).
#12
enjoy-digital
opened
2 years ago
0
Fix and improve the NVIDIA free callback
#11
maleadt
closed
2 years ago
0
GPL incompatibilities
#10
maleadt
closed
2 years ago
1
Unknown bug in GPU buffer handling
#9
maleadt
closed
2 years ago
0
Improved LMS7002M PHY (now with internal TX/RX Delay).
#8
enjoy-digital
closed
2 years ago
2
LimeSuiteGUI: Implement Reset/Default.
#7
enjoy-digital
closed
2 years ago
1
Dump LMS7002M configuration when fully initialized with Fairwaves' software.
#6
enjoy-digital
closed
2 years ago
1
Test the full digital chain over PCIe.
#5
enjoy-digital
opened
2 years ago
1
Design/Test LMS7002M/FPGA Digital Interface.
#4
enjoy-digital
opened
2 years ago
3
Enable/Check TCXO clock.
#3
enjoy-digital
closed
2 years ago
3
Figure out I2C topology on the two I2C buses and get it working.
#2
enjoy-digital
closed
2 years ago
5
Configure Board's PMICs.
#1
enjoy-digital
closed
2 years ago
5