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fpga-open-speech-tools
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simulink_models
Simulink models for speech and audio processing
MIT License
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Initial Commit of Dylan's S3 Upload Script
#47
dack-fe
closed
3 years ago
2
Added vector gain model
#46
fe-wickham
closed
3 years ago
0
Updated Simple Gain model to new framework with channel based processing
#45
fe-wickham
closed
3 years ago
0
AES
#44
fe-wickham
closed
4 years ago
3
support for dtogen being in simulink_codegen
#43
tvannoy
closed
4 years ago
0
Noise suppression
#42
audiologic-vannoy
closed
4 years ago
1
Updated model.json to have processing option
#41
fe-wickham
closed
4 years ago
0
Simple gain can now actually be a gain
#40
fe-wickham
closed
4 years ago
3
Add vectorized model support
#39
tvannoy
closed
4 years ago
0
FFT Analysis/Synthesis Example
#38
rksnider
closed
4 years ago
2
Set up github actions
#37
tvannoy
closed
3 years ago
2
Autogen framework
#36
fe-wickham
closed
4 years ago
8
Zero config path
#35
fe-wickham
closed
4 years ago
2
Zero Config: Path Setup
#34
fe-wickham
closed
4 years ago
0
Noise suppression model discussion
#33
audiologic-vannoy
closed
4 years ago
3
Update copyright
#32
audiologic-vannoy
closed
4 years ago
1
Removed unnecessary project files
#31
fe-wickham
closed
4 years ago
0
Added Python running out of process
#30
fe-wickham
closed
4 years ago
0
merge dev
#29
tvannoy
closed
4 years ago
0
Updated echo, flanger, and bitcrusher to use enable rather than bypass registers
#28
fe-wickham
closed
4 years ago
1
Added Matlab projects
#27
fe-wickham
closed
4 years ago
0
pFIR_Testing
#26
JustinWilliamsMSU
closed
3 years ago
2
Conv reverb
#25
asalois
closed
4 years ago
1
Support multiple register values during simulation
#24
tvannoy
closed
4 years ago
1
Auditorynerve hezekiah
#23
AjaxAustin
closed
4 years ago
0
Init fixing
#22
BaileyGalacci
closed
4 years ago
1
delay and sum beamformer
#21
tvannoy
closed
4 years ago
1
Refactor init scripts
#20
audiologic-vannoy
closed
4 years ago
6
Add support for autogenerating UI configuration
#19
audiologic-vannoy
closed
4 years ago
1
Dynamic compression demo
#18
tvannoy
closed
4 years ago
1
Simple noise reduction
#17
tvannoy
closed
4 years ago
0
Change bypass to enable
#16
audiologic-vannoy
closed
4 years ago
2
Windows setup improvement
#15
rksnider
closed
4 years ago
1
Remove generated html files
#14
tvannoy
opened
4 years ago
0
Convert models to use Simulink Projects
#13
tvannoy
closed
4 years ago
1
Echo VHDL
#12
tvannoy
closed
4 years ago
0
finished bitcrusher
#11
audiologic-vannoy
closed
4 years ago
0
Don't show verification output when generating vhdl
#10
audiologic-vannoy
closed
4 years ago
1
Flanger
#9
audiologic-vannoy
closed
4 years ago
1
udpate HDL workflow advisor
#8
audiologic-vannoy
closed
4 years ago
1
Add sign bit to model parameters
#7
tvannoy
closed
4 years ago
0
Use a map for register definitions
#6
tvannoy
opened
4 years ago
0
Change system clock name
#5
tvannoy
closed
4 years ago
0
Script register data type conversions
#4
tvannoy
closed
4 years ago
1
Bypass register should be register 0
#3
tvannoy
closed
4 years ago
1
Add wet/dry mix control to bitcrusher model
#2
tvannoy
closed
4 years ago
0
Bitcrusher
#1
rksnider
closed
4 years ago
2
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