jameshanlon netlist-paths issues

jameshanlon / netlist-paths

A library and command-line tool for querying a Verilog netlist.

https://jameshanlon.github.io/netlist-paths

Apache License 2.0

26 stars 3 forks source link

issues

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Unrecognised nodes

#29 jameshanlon opened 2 years ago
0
Add support for specifying only through points as waypoints

#28 jameshanlon opened 2 years ago
0
add --top-module option

#27 heiner-bauer closed 2 years ago
2
test passing multiple files

#26 heiner-bauer closed 2 years ago
1
Investigate alternative wildcard matching algorithm

#25 jameshanlon opened 2 years ago
0
Pass includes and defines from Python

#24 heiner-bauer closed 2 years ago
1
Introduce more exception types

#23 jameshanlon opened 2 years ago
0
Run tests with Clang sanitizers

#22 jameshanlon opened 2 years ago
0
Tidy headers with include what you use

#21 jameshanlon opened 2 years ago
0
Add support for bitwise connectivity

#20 jameshanlon opened 2 years ago
0
Consider using magic_enum

#19 jameshanlon opened 2 years ago
0
Add a facility to compile Verilog from a string

#18 jameshanlon opened 2 years ago
0
Improve dotfile dump with better annotations

#17 jameshanlon opened 2 years ago
0
Verilator cannot inline interfaces

#16 jameshanlon opened 2 years ago
0
Add option to dump named start/end points for fainin/fanout queries

#15 jameshanlon opened 2 years ago
0
Don’t list internal verilator nodes in reports

#14 jameshanlon opened 2 years ago
0
Identify port types

#13 jameshanlon closed 2 years ago
1
Create a path object and refactor unit tests

#12 jameshanlon closed 2 years ago
1
Self paths

#11 jameshanlon opened 2 years ago
2
Top-level ports appear twice

#10 jameshanlon closed 2 years ago
1
Add an option to report all named data types in the design

#9 jameshanlon closed 2 years ago
1
Expand XML parser handling of node types

#8 jameshanlon closed 3 years ago
0
Package function returning a constant has no scope

#7 jameshanlon closed 3 years ago
2
Performance issues with large graphs

#6 jameshanlon opened 3 years ago
0
Register identification should check for sensitivity to a clock edge

#5 jameshanlon opened 3 years ago
0
Add options to relax path start and end constraints

#4 jameshanlon closed 3 years ago
0
Consider supporting Verible or Surelog as alternative to Verilator

#3 mithro opened 3 years ago
1
fatal: clone of 'git@github.com:jameshanlon/verilator.git'

#2 psychedel closed 5 years ago
1
shared_array assertion

#1 jameshanlon closed 3 years ago
0