jdryg tis100cpu issues - Githubissues

jdryg / tis100cpu

TIS-100 CPU in VHDL

MIT License

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issues

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Generic Instruction Memory entity

#7 jdryg closed 9 years ago
0
Feature proposal: Node performance counters

#6 holmak opened 9 years ago
2
Observe correct limits on register values: -999 to 999

#5 holmak opened 9 years ago
1
Read after Write bug

#4 jdryg closed 9 years ago
1
Remove port instructions

#3 jdryg opened 9 years ago
2
SWP in ALU

#2 jdryg closed 9 years ago
1
Cycle-accurate design

#1 jdryg opened 9 years ago
5