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**Which problem is this feature request solving?**
Instance, net, and reg in the VSCode outline use the same icons, making them difficult to distinguish.
This forces me to look at the small prin…
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This evokes syntax error as shown (both iverilog 11.0 and 12.0, with -g1800-2005 and without):
> assign ws3 = KPU_Test_types::array_of_5_Tup2_220_cons ( { 3'd0 , { KPU_Test_types::array_of_4_logic…
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Hi!
Multiple packed array dimensions are system verilog feature. Yet following code compiles fine with -g2005 flag.
```verilog
module test(input [3:0][7:0] i, output [31:0] q);
assign q …
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**Describe the bug**
Hi,
I have the following clock gating cell:
```
`timescale 1ps/1ps
module clk_gate_and #(
parameter G_FPGA_TYPE = "BUFG" // bypass clock gate for FPGA target
) (
…
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The list of languages that Pieces supports is hidden away in the FAQ section of the website. It would be good to have them listed somewhere in the docs - where they would go is pretty ambiguous. My re…
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- [x] Replace verilog backend with verilogAST
- [x] Replace metadata["verilog"] with concrete verilogAST definition
- [ ] Replace verilog definitions of coreir/corebit with verilogAST
- [ ] Linking…
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Hello!
SystemVerilog added the system tasks `$fatal`, `$error`, `$warning`, and `$info` (20.10). However, sv2v does not convert them at all, causing Verilog tools to fail. It would be nice to conve…
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What curious if the team would consider directly supporting a `pre-commit` hook based on https://pre-commit.com/#creating-new-hooks ?
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Environments
```
operating system WSL Ubuntu 20.04
cocotb version 1.8.1 (installed from pip)
verilator version 5.023 devel rev v5.020-176-g953249aa4 (built from source)
python version 3.10.14…
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Verilator Overview [Reference](https://colab.research.google.com/github/byuccl/digital_design_colab/blob/master/Tutorials/verilator_overview/verilator_overview.ipynb) and Verilog with VS Code [Referen…