lerwys bpm-sw-old-backup issues

lerwys / bpm-sw-old-backup

Main repository for the BPM firmware and software

GNU Lesser General Public License v3.0

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issues

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[wb_fmc130m_4ch] Add switching clock through MMCX connector

#32 lerwys opened 10 years ago
0
[wb_acq_core] Add multiple "simultaneous" acquisition paths

#31 lerwys opened 10 years ago
0
[wb_acq_core] Cleanup core and implement missing features

#30 lerwys opened 10 years ago
0
[pcie-core] Fix missing signal

#29 lerwys closed 10 years ago
1
[ddr3-sdram] phy_init_done never asserted

#28 lerwys closed 11 years ago
2
[fmc-adc-data] Check registers in the datapath to ease timing

#27 lerwys opened 11 years ago
0
[emb-sw] Consider moving the emb-sw folder to another git repository

#26 lerwys opened 11 years ago
0
[fmc-adc-common] Fix BUFIO/BUFR/BUFG clk generation

#25 lerwys closed 11 years ago
1
[soon-to-be fmc-port] Add g_with_bufio and g_with_bufr

#24 lerwys closed 11 years ago
1
Reimplement emb-sw fmc structures!

#23 lerwys opened 11 years ago
0
[fmc-516] Clean wb_fmc516 delay interface

#22 lerwys closed 11 years ago
1
[ddr3-core] Implement a DDR3 core wrapper for Xilinx MIG

#21 lerwys closed 10 years ago
3
[all] Unify SDB descriptors.

#20 lerwys opened 11 years ago
0
[dsp-devel][fmc516] ADC Data appears to be off by one cycle

#19 lerwys opened 11 years ago
2
[fmc516] fix multiple MMCM primitives in adc_clock.vhd

#18 lerwys closed 11 years ago
1
[fmc516] Implement automatic idelay selection

#17 lerwys opened 11 years ago
0
[fmc516] Implement synchronization between all data chains with a single clock domain

#16 lerwys closed 11 years ago
2
[fmc516] Fix reserved register fields

#15 lerwys opened 11 years ago
0
[fmc516-sw] Support for multiple fmc516 cores (and boards...)

#14 lerwys opened 11 years ago
0
[fmc516] Delay the falling edge data from the IDDR primitive

#13 lerwys closed 11 years ago
1
change SPI three mode interface to miso/mosi/out_en

#12 lerwys closed 11 years ago
1
[FMC516] Check SPI communication

#11 lerwys closed 11 years ago
1
[fmc516] Check ADC clock & MMCM values

#10 lerwys opened 11 years ago
1
[ethernet/ebone] Implement mux for ethernet packages?

#9 lerwys opened 11 years ago
0
Fix wrong xwb_fmc516 component declaration in custom_wishbone.vhd file

#8 lerwys closed 11 years ago
1
Reorganize the dbe_bpm_fmc516 top files

#7 lerwys closed 11 years ago
1
[fmc516] Select the appropriate delays to clock and data coming from ADC

#6 lerwys closed 11 years ago
3
Insert CLOCK_DEDICATED_ROUTE=FALSE constraint to .ucf

#5 lerwys closed 11 years ago
1
Replace IBUFGDS to IBUFDS

#4 lerwys closed 11 years ago
1
Implement ADC Reset and Reset Clk Div

#3 lerwys closed 11 years ago
2
Make wb_stream more generic

#2 lerwys closed 11 years ago
1
[ebone] Add etherbone support

#1 lerwys opened 11 years ago
1