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lip6
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coriolis
Coriolis VLSI EDA Tool (LIP6)
https://coriolis.lip6.fr
GNU General Public License v2.0
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Coriolis put a cells on another cell
#133
ip-arch
opened
1 month ago
0
Fixed misaligned cells.
#132
lanserge
closed
4 months ago
1
Fix: output info layer selected for text label if found with the same gds2layer
#131
lanserge
closed
4 months ago
1
Fixed pad spacing calculation
#130
lanserge
closed
4 months ago
1
Added layer map manupulation functions to LefImport
#129
lanserge
closed
4 months ago
5
Fix cell path in designflow.technos for lsxlib.
#128
jpc-lip6
closed
4 months ago
1
Fix macro pin non pref
#127
jpc-lip6
closed
4 months ago
1
Fixes for AREF GDS parser
#126
lanserge
closed
5 months ago
1
Try use different action for deploying github pages
#125
robtaylor
closed
5 months ago
1
Make only-docs logic more obvious
#124
robtaylor
closed
5 months ago
1
Revert Pull Request target
#123
robtaylor
closed
5 months ago
3
macro: Ad-hoc patch fix power pin conflict for GF180 SRAMs
#122
gatecat
closed
5 months ago
0
macro: Fix naming of wrapper
#121
gatecat
closed
5 months ago
0
GDS parse fixes (text layer to have datatype and aref bug)
#120
lanserge
closed
5 months ago
2
naming: Never remove underscores from original name
#119
gatecat
opened
5 months ago
9
Try fix docs
#118
robtaylor
closed
5 months ago
0
Never **ever** remove ${HOME}/.local again!
#117
jpc-lip6
closed
5 months ago
0
Attempt to fix doc generation issues with links
#116
robtaylor
closed
5 months ago
0
Attempt to fix documentation build issues
#115
robtaylor
closed
5 months ago
0
Create a new hierarchy level to wrap macros
#114
gatecat
closed
5 months ago
1
Fix gds parser gf180 sram
#113
jpc-lip6
closed
5 months ago
0
htree: Fix leaf contact selection
#112
gatecat
closed
5 months ago
0
htree: Fix a tiny typo
#111
gatecat
closed
5 months ago
0
Rebase analog fixes
#110
jpc-lip6
closed
5 months ago
0
docs: switch to pull_request_target
#109
gatecat
closed
5 months ago
0
cumulus: Allow macros with MY orientation
#108
gatecat
closed
5 months ago
0
Set write-all permission for ghpages workflow
#107
robtaylor
closed
6 months ago
1
anabatic: Fix connectivity for staircases
#106
gatecat
closed
6 months ago
0
Turn has more than one horizontal segment. / Turn is missing mandatory horizontal segment. followed by segfault
#105
gatecat
closed
6 months ago
1
Meson: remove old build system artifacts
#104
Coloquinte
closed
6 months ago
1
DRC regression on tests
#103
Coloquinte
opened
6 months ago
0
wheel artefacts not appearing
#102
robtaylor
opened
6 months ago
0
Alternate link fix
#101
robtaylor
closed
5 months ago
1
LEF pins causing misaligned Horizonal/Verticals and power via generation
#100
gatecat
closed
5 months ago
2
Safer configuration
#99
Coloquinte
opened
7 months ago
0
Fix build wheels linking to libpython3.6
#98
robtaylor
closed
6 months ago
1
[Verilog netlist export] Fix for cell net names with indexes be in proper Verilog format
#97
lanserge
closed
7 months ago
1
Fixed Verilog netlist export with presence of unconnected plugs
#96
lanserge
closed
7 months ago
1
Support for extended BLIF attributes
#95
gatecat
opened
7 months ago
4
GDS: Actually skip discarded text
#94
gatecat
closed
7 months ago
0
Get version from git tag
#93
robtaylor
closed
7 months ago
2
Minor doc changes for Katana
#92
Coloquinte
closed
7 months ago
1
Fixes for release 2 5 5
#91
jpc-lip6
closed
7 months ago
1
Move website to coriolis-eda.org
#90
robtaylor
opened
7 months ago
0
Publishing of main branch wheels to test PyPi is not working
#89
rossmotley
closed
7 months ago
2
Make Python package version dynamic
#88
rossmotley
closed
7 months ago
2
Failures in PyPi uploads should fail workflows
#87
rossmotley
closed
7 months ago
0
Failure to upload to test pypi on main shows as success
#86
robtaylor
closed
7 months ago
2
Fix links in README
#85
rossmotley
closed
7 months ago
0
Filter out redundant plugs that have no connection inside cell while export Verilog netlist
#84
lanserge
closed
8 months ago
0
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