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louieb117
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Network-Microprocessor-FPGA-Project
MIT License
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Close #25: created the SLT feature to the ALU.
#37
louieb117
closed
1 year ago
0
Close #18: created testbench and enhanced existing modules.
#36
louieb117
closed
1 year ago
0
Create Memory Map
#35
louieb117
opened
1 year ago
0
Comment source code
#34
louieb117
opened
1 year ago
0
A descriptive paragraph for each top level function
#33
louieb117
opened
1 year ago
0
Track hours worked
#32
louieb117
opened
1 year ago
0
Complete Timing analysis for Memory IC, Processor, and FPGA
#31
louieb117
opened
1 year ago
0
Create Processor Code
#30
louieb117
opened
1 year ago
0
Create top level State machine
#29
louieb117
opened
1 year ago
0
Create top level module to connect all Major Verilog modules
#28
louieb117
opened
1 year ago
0
Create Address Decode and Control Logic modules
#27
louieb117
opened
1 year ago
0
Create ARP Processor Verilog Modules
#26
louieb117
opened
1 year ago
0
Enhance ALU module
#25
louieb117
closed
1 year ago
0
Create simulate road block list
#24
louieb117
closed
1 year ago
1
Create Todo List for Final Report
#23
louieb117
closed
1 year ago
1
Enhance Diagram for ARP PP
#22
louieb117
opened
1 year ago
0
Enhance Diagrams for Address Decide and Control Logic
#21
louieb117
opened
1 year ago
0
Create High Level Description of project
#20
louieb117
closed
1 year ago
1
Close #15: updated data path file with new modules
#19
louieb117
closed
1 year ago
0
Create data path test bench
#18
louieb117
closed
1 year ago
0
Create Control Unit Test Bench
#17
louieb117
closed
1 year ago
0
Create Control Unit module
#16
louieb117
closed
1 year ago
1
Update Data Path source file
#15
louieb117
closed
1 year ago
0
Create Program Counter Test Bench
#14
louieb117
closed
1 year ago
0
Create Instruction Memory Test Bench
#13
louieb117
closed
1 year ago
1
Create Multiplexer Test Bench
#12
louieb117
closed
1 year ago
1
Create ALU Test Bench
#11
louieb117
closed
1 year ago
0
Create Data Memory Test Bench
#10
louieb117
closed
1 year ago
1
Create Register File Test Bench
#9
louieb117
closed
1 year ago
1
Review Verilog for current progress
#8
louieb117
closed
1 year ago
1
Create simple block diagram of FPGA internal design
#7
louieb117
closed
1 year ago
1
Push old Single Cycle Processor code
#6
louieb117
closed
1 year ago
1
Research Packet Processing
#5
louieb117
closed
1 year ago
1
Review Single Cycle Processor
#4
louieb117
closed
1 year ago
0
Create stretch goal list
#3
louieb117
closed
1 year ago
1
Create features list of initial version
#2
louieb117
closed
1 year ago
2
Create simple block diagram of FPGA internal design
#1
louieb117
closed
1 year ago
5