michaeljclark rv8 issues

michaeljclark / rv8

RISC-V simulator for x86-64

https://michaeljclark.github.io/

MIT License

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issues

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Add per instruction cycle metadata for cycle count approximation

#18 michaeljclark opened 7 years ago
0
Implement simple RV{32,64,128} test-assembler

#17 michaeljclark closed 7 years ago
1
compress-elf static translation and relocation for well formed subset of static PIE ELF

#16 michaeljclark opened 7 years ago
0
Add output buffering, labels, relocation and execution to the JIT API

#15 michaeljclark opened 7 years ago
0
Add typesafe variadic template printf with u128/s128/f128 support

#14 michaeljclark opened 7 years ago
1
Implement additional proxy syscalls

#13 michaeljclark opened 7 years ago
0
Implement optimized operand immediate decoder (PEXT/PDEP)

#12 michaeljclark opened 7 years ago
0
Implement alternative LaTeX instruction table generator

#11 michaeljclark opened 7 years ago
0
Add Berkeley SoftFloat to support RV{32,64,128}Q

#10 michaeljclark opened 7 years ago
0
Implement standard operator overloads for u128 and s128

#9 michaeljclark closed 7 years ago
1
Implement compiler agnostic u128 and s128 div{u} and rem{u}

#8 michaeljclark opened 7 years ago
1
Add byte order macros to emu/riscv-{machine,pte}.h

#7 michaeljclark opened 7 years ago
0
Decoder performance experiment

#6 michaeljclark closed 7 years ago
2
Implement address translation in emu/riscv-mmu.h

#5 michaeljclark closed 7 years ago
1
Add (draft) ELF128 definitions

#4 michaeljclark opened 7 years ago
1
Add riscv128 opcodes

#3 michaeljclark closed 7 years ago
1
Fix encodings for v1.9 system instructions

#2 acw1251 closed 8 years ago
1
Add travis automated encode/decode regression tests

#1 michaeljclark opened 8 years ago
0