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mosscomp
/
moss
A computer for human beings.
https://mosscomp.com
Apache License 2.0
40
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2
forks
source link
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Setup verible linting config and fix warning
#49
hasheddan
closed
9 months ago
0
Document editor setup
#48
hasheddan
opened
9 months ago
1
Run linter in CI
#47
hasheddan
opened
9 months ago
0
Add initial control unit with RV32I instructions
#46
hasheddan
closed
8 months ago
0
Consider moving to non-project mode in Vivado
#45
hasheddan
opened
9 months ago
0
Send LSB first in UART transmitter
#44
hasheddan
closed
10 months ago
0
Add vivado development workflow docs
#43
hasheddan
opened
10 months ago
0
Update to Vivado v2023.1
#42
hasheddan
closed
10 months ago
0
Fix link to OpenTitan RISC-V Assembly Style Guide
#41
hasheddan
closed
10 months ago
0
Implement initial RV64I core
#40
hasheddan
opened
1 year ago
0
Add simulation for register file
#39
hasheddan
closed
1 year ago
0
Add .ccls config for LSP features in sim
#38
hasheddan
closed
1 year ago
0
Implement 64-bit register file
#37
hasheddan
closed
1 year ago
0
Mosscomp.com down?
#36
mithro
closed
1 year ago
2
Start learn section of documentation with term list
#35
hasheddan
closed
1 year ago
0
Simulation does not consider nested RTL modules
#34
hasheddan
opened
1 year ago
0
Add UART receiving module
#33
hasheddan
closed
1 year ago
0
Move JTAG to dedicated docs and add content
#32
hasheddan
closed
1 year ago
0
Fix UART transmission
#31
hasheddan
closed
1 year ago
0
Add initial protocols documentation
#30
hasheddan
closed
2 years ago
0
Add simulation section and clean up os section of Makefile
#29
hasheddan
closed
2 years ago
0
Add verilator testbench for ALU module
#28
hasheddan
closed
2 years ago
0
Add initial moss README.md
#27
hasheddan
closed
2 years ago
0
Add basic 64-bit ALU
#26
hasheddan
closed
2 years ago
0
Add style section to CONTRIBUTING.md
#25
hasheddan
closed
2 years ago
0
Add machinery for building, emulation, and debugging of MossOS
#24
hasheddan
closed
2 years ago
0
Add trace flag to verilator command
#23
hasheddan
closed
3 years ago
0
Only run verilator when rtl or sim changes
#22
hasheddan
closed
3 years ago
1
Add QEMU RV64 setup steps
#21
hasheddan
closed
3 years ago
0
Skip verilator CI step if rtl not modified
#20
hasheddan
closed
3 years ago
1
Remove extraneous verilator commands in CONTRIBUTING.md
#19
hasheddan
closed
3 years ago
0
Update README.md with project overview
#18
hasheddan
closed
2 years ago
0
Update ci workflow to be compatible with older verilator versions
#17
hasheddan
closed
3 years ago
0
Verilator step fails in CI workflow
#16
hasheddan
closed
3 years ago
1
Add GH actions CI workflow
#15
hasheddan
closed
3 years ago
0
Restructure directory tree
#14
hasheddan
closed
3 years ago
0
Use localparam for uart states
#13
hasheddan
closed
3 years ago
0
Add initial Verilator setup and CONTRIBUTING.md
#12
hasheddan
closed
3 years ago
0
Add CONTRIBUTING.md
#11
hasheddan
closed
3 years ago
0
Add initial verilator testbenches
#10
hasheddan
closed
1 year ago
1
Implement UART module
#9
hasheddan
closed
3 years ago
0
Implement UART module for communicating of Arty USB-UART interface
#8
hasheddan
closed
1 year ago
2
Remove duplicate clock signal in arty a7 constraints
#7
hasheddan
closed
3 years ago
0
Parameterize Vivado .xpr files
#6
hasheddan
opened
3 years ago
1
Add vivado toolchain documentation
#5
hasheddan
opened
3 years ago
1
Add initial vivado toolchain setup
#4
hasheddan
closed
3 years ago
0
Add Apache 2.0 license
#3
hasheddan
closed
3 years ago
0
Design logo / branding assets
#2
hasheddan
closed
1 year ago
1
Create initial BOM
#1
hasheddan
opened
3 years ago
0