open-ephys rhythm issues - Githubissues

open-ephys / rhythm

Intan Technologies Rhythm Verilog HDL code

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issues

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XEM7310 bitfiles

#15 mcjpedro opened 2 years ago
4
Usb3 verilog modifications to allow for TTL pulse train generation

#14 paulmthompson opened 2 years ago
6
Feature request: precise TTL output control from the Open Ephys aquisition board

#13 paulmthompson closed 2 years ago
3
OE board's LEDs should default to off

#16 jonnew opened 8 years ago
3
USB3 glitching issues

#12 allenyin opened 8 years ago
3
Addition of user programmable clock sync

#11 jonnew closed 8 years ago
5
Implement daisy-chaining

#10 jvoigts opened 10 years ago
0
Enable channel subsampling at >30Khz

#9 jvoigts opened 10 years ago
0
Digital Events do not seem to be written to disk in a resonable amount of time

#8 parityviolation opened 10 years ago
5
Bitfile is not working on XEM6010-LX150

#7 jvoigts opened 10 years ago
1
USB3 branch test and integrate

#6 ckemere opened 10 years ago
1
Maybe re-organize files to make switching between windows/linux easier?

#5 ckemere opened 10 years ago
0
Interfacing LabVIEW FPGA modules with Intan Verilog code

#4 alexbw opened 10 years ago
2
Display proper data on status LEDs

#3 jvoigts opened 11 years ago
0
add code to control status LEDs

#2 jvoigts closed 11 years ago
1
adapt ADC control to work with the TI ADS8325

#1 jvoigts closed 11 years ago
1