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os-fpga
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RTL_Benchmark
This repository contains the benchmarks.
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Added new BRAM testcases
#115
AYYAZmayo
closed
4 months ago
0
Added new BRAM design EDA-2755
#114
AYYAZmayo
closed
5 months ago
0
Updated directory paths
#113
AYYAZmayo
closed
6 months ago
0
Updated the directory structure of BRAM/DSP validation suites
#112
AYYAZmayo
closed
6 months ago
0
Added new BRAM testcases
#111
AYYAZmayo
closed
7 months ago
0
Added new BRAM testcase
#110
AYYAZmayo
closed
8 months ago
0
Added new BRAM testcases
#109
AYYAZmayo
closed
8 months ago
0
Added new testcase EDA-2414-bram-initialization
#108
AYYAZmayo
closed
8 months ago
0
new EDA-2292
#107
ayyazahmed-rs
closed
10 months ago
0
updated clockedge from pos to negedge
#106
ayyazahmed-rs
closed
10 months ago
0
updated .ys
#105
awaisabbas-rs
closed
10 months ago
0
Extra Designs are removed from Repo
#104
komalinayat
closed
9 months ago
0
fixed errors
#103
komalinayat
closed
11 months ago
1
resolved the duplicated .v and .sv files issue in some designs
#102
ayyazahmed-rs
closed
11 months ago
0
files are updated
#101
komalinayat
closed
1 year ago
0
Updated tb files
#100
ayyazahmed-rs
closed
1 year ago
0
Added three new BRAM-Jira testcases to bram_suite
#99
ayyazahmed-rs
closed
1 year ago
0
New DSP designs are added
#98
komalinayat
closed
1 year ago
0
Yosys validation
#97
awaisabbas-rs
closed
1 year ago
0
DSP validtion designs added
#96
awaisabbas-rs
closed
1 year ago
0
EDA-1415_fix
#95
ayyazahmed-rs
closed
1 year ago
0
Testcases for EDA-348 are added
#94
awaisabbas-rs
closed
1 year ago
0
Removed typo in tb.sv
#93
ayyazahmed-rs
closed
1 year ago
0
New Testcases for Yosys Validation are Added
#92
awaisabbas-rs
closed
1 year ago
0
Removed unsupported pattern
#91
lilitrs
closed
1 year ago
0
Added BRAM tests
#90
lilitrs
closed
1 year ago
1
EDA-1318_testcase is added
#89
ayyazahmed-rs
closed
1 year ago
0
asymmetric BRAM EDA jira suite added
#88
ayyazahmed-rs
closed
1 year ago
0
Bhavya's bcpu design added
#87
awaisabbas-rs
closed
1 year ago
2
New testcases for yosys validation are added
#86
awaisabbas-rs
closed
1 year ago
1
Changed the post_synth file name
#85
lilitrs
closed
1 year ago
0
Added new BRAM test cases
#84
lilitrs
closed
1 year ago
2
Testcases against EDA-1168 are added
#83
awaisabbas-rs
closed
1 year ago
0
adding aes_256 top module against EDA-1091
#82
awaisabbas-rs
closed
1 year ago
4
Added yosys validation DSP tests.
#81
aram-rs
closed
1 year ago
0
Testcases for yosys vaidation are added
#80
awaisabbas-rs
closed
1 year ago
0
DSP designs are added
#79
komalinayat
closed
1 year ago
0
clocks names are updated in clock tree design
#78
awaisabbas-rs
closed
1 year ago
0
Added missing file from previous commit.
#77
Lia-rs
closed
2 years ago
0
Added EPFL benchmarks (Verilog and VHDL).
#76
Lia-rs
closed
2 years ago
0
Missin module is added
#75
komalinayat
closed
2 years ago
0
Module update
#74
komalinayat
closed
2 years ago
0
Vtr update
#73
komalinayat
closed
2 years ago
1
Missing designs are added
#72
awaisabbas-rs
closed
2 years ago
4
full_case parallel_case added for conv2d design
#71
awaisabbas-rs
closed
2 years ago
4
Added design27 random Verilog test case.
#70
baghdasaryanbella
closed
2 years ago
0
DSP_designs are updated
#69
komalinayat
closed
2 years ago
0
New_DSP_Designs
#68
komalinayat
closed
2 years ago
0
DSP_Designs are updated
#67
komalinayat
closed
2 years ago
0
Applied 'RS-Golden-Suite' branch modifications.
#66
aram-rs
closed
2 years ago
2
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