issues
search
os-fpga
/
yosys_verific_rs
Yosys + (Optional) Verific Integration
Other
5
stars
6
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Submodules Update Fix EDA-3310
#817
AYYAZmayo
opened
4 days ago
0
Fix EDA-3310/Submodule update
#816
AYYAZmayo
closed
4 days ago
0
Update install_centos_dependencies_build.sh to python3-devel
#815
NadeemYaseen
closed
5 days ago
0
Adding support for multi-bit constants in IO primitives' port connections
#814
behzadmehmood
closed
1 week ago
0
Revert "Submodule Update Release_Sim_1.6.0"
#813
AYYAZmayo
closed
4 days ago
0
Submodule Update Release_Sim_1.6.0
#812
AYYAZmayo
closed
1 week ago
0
Adding fix for EDA-3287 and EDA-3307
#811
awaisabbas006
closed
1 week ago
0
Release_Sim_1.5.8
#810
AYYAZmayo
closed
2 weeks ago
0
Netlist Checker
#809
behzadmehmood
closed
2 weeks ago
0
Submodule update Fix EDA-3283/EDA-3304
#808
AYYAZmayo
closed
3 weeks ago
0
Release_Sim_1.5.7
#807
AYYAZmayo
closed
4 weeks ago
0
Removing extra wires from fabric netlist
#806
behzadmehmood
closed
4 weeks ago
0
Removing I_FAB/O_FAB primitives
#805
behzadmehmood
closed
1 month ago
0
Import stmt fix
#804
alaindargelas
closed
1 month ago
0
New flow to determine control signals
#803
chungshien-chai
closed
1 month ago
0
Blocking stmt ram infer
#802
alaindargelas
closed
1 month ago
0
Support writing CLK pin XML
#801
chungshien-chai
closed
1 month ago
0
Update yosys to 0.44 and synlig to chipsalliance version
#800
alaindargelas
closed
1 month ago
0
Update Yosys-0.44
#799
awaisabbas006
closed
1 month ago
2
Reverted Sim_release_1.5.4
#798
AYYAZmayo
closed
1 month ago
0
Release_sim_1.5.4
#797
AYYAZmayo
closed
1 month ago
1
Fix EDA-3248/EDA-3262
#796
AYYAZmayo
closed
1 month ago
0
Submodule update
#795
AYYAZmayo
closed
1 month ago
0
Fix, EDA-3177, Submodule update
#794
AYYAZmayo
closed
1 month ago
1
Submodule update
#793
AYYAZmayo
closed
1 month ago
0
Submodule update fix-EDA-3246: Converting O_BUF_DS to O_BUFT_DS
#792
AYYAZmayo
closed
1 month ago
0
Update status
#791
chungshien-chai
closed
1 month ago
1
submodule update fix EDA-3175
#790
AYYAZmayo
closed
1 month ago
0
Update design editor config.json flow after extra wires are removed
#789
chungshien-chai
closed
1 month ago
1
Cleaning wrapper module after flattening
#788
behzadmehmood
closed
1 month ago
0
Improve output port trait handling
#787
chungshien-chai
closed
1 month ago
0
Revert eda_3175 Data signals
#786
alaindargelas
closed
1 month ago
0
Submodule update/EDA-3175: add extra cell/ports to add O_FAB
#785
AYYAZmayo
closed
1 month ago
0
Update CI.yml
#784
NadeemYaseen
opened
1 month ago
0
Adding pass through LUTs before handling dangling wires.
#783
behzadmehmood
closed
1 month ago
2
fix partially EDA-3175, avoid cascade of O_FAB
#782
alaindargelas
closed
1 month ago
0
fix volatile char pointer bug
#781
alaindargelas
closed
2 months ago
0
Add init of uninitialized regs
#780
alaindargelas
closed
2 months ago
0
EDA-3186 FCLK_BUF wrong insertion
#779
AYYAZmayo
closed
2 months ago
0
Handling interface primitives connected to BUFs
#778
behzadmehmood
closed
2 months ago
0
Support PLL VCO output
#777
chungshien-chai
closed
2 months ago
0
Support non-clock-naming pin as core clock
#776
chungshien-chai
closed
2 months ago
0
EDA-977 gate_clock_conversion
#775
AYYAZmayo
closed
2 months ago
0
Fixing code for port re-ordering
#774
behzadmehmood
closed
2 months ago
0
Revert obs clean comment
#773
alaindargelas
closed
2 months ago
0
Data signal to fabric for INOUT port
#772
chungshien-chai
closed
2 months ago
0
Handling inout port after flattening wrapper
#771
behzadmehmood
closed
2 months ago
1
Fix EDA-3157, information in netlist_info.json
#770
AYYAZmayo
closed
2 months ago
0
revert obs_clean in plugin
#769
awaisabbas006
closed
2 months ago
0
Submodule update
#768
AYYAZmayo
closed
2 months ago
0
Next