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pulp-platform
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cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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Potential combinational loop with `RegAmoPostCut=0`
#107
paulsc96
opened
7 months ago
0
treewide: Various build and documentation fixes
#106
paulsc96
closed
7 months ago
0
target/xilinx: Clean up flow, multi-board support, add VCU128
#105
paulsc96
closed
7 months ago
0
treewide: Add Ethernet peripheral
#104
chaoqun-liang
opened
7 months ago
0
target/sim: Add JTAG tasks for reg access and preloading
#103
alex96295
closed
7 months ago
4
treewide: Add clic virtualization support
#102
alex96295
opened
8 months ago
1
Astral rebase
#101
yvantor
closed
7 months ago
3
cheshire_top_xilinx: Re-align cheshire_cfg
#100
niwis
closed
7 months ago
2
deps: Update `cva6` to pulp-v1.0.0
#99
niwis
closed
7 months ago
0
deps: Update `axi_riscv_atomics` to v0.8.2
#98
niwis
closed
8 months ago
1
deps: Update `unbent` to v0.1.6
#97
niwis
closed
8 months ago
0
hw: Remove outdated comment
#96
niwis
closed
8 months ago
0
sw: Add parameter for default boot baudrate
#95
paulsc96
closed
8 months ago
0
Reworked FPGA flow for multi board / flavor support
#94
CyrilKoe
closed
7 months ago
3
Update Docker flow
#93
disdi
opened
10 months ago
2
Issues found when building cheshire
#92
TheSmolBoi
closed
7 months ago
3
treewide: Add SpinalHDL USB 1.1 controller
#91
thommythomaso
closed
3 months ago
0
docs: Correct Questa compile script name
#90
TheSmolBoi
closed
8 months ago
1
treewide: Fix submodule protocol, some RTL cleanup
#89
paulsc96
closed
10 months ago
0
CVA6-SDK Submodule requires a github account with added SSH/GPG key
#88
TheSmolBoi
closed
10 months ago
2
target/sim: Fix serial link address alignment
#87
alex96295
closed
10 months ago
0
hw: Fix Regbus address range in AXI crossbar
#86
alex96295
closed
10 months ago
0
sw: Support bare-metal SMP in software stack
#85
emanueleparisi
opened
11 months ago
0
hw: Disable AXI splitting checks in AXI-RT
#84
thommythomaso
closed
12 months ago
1
Draft: Boost RTC frequency to support Linux boot.
#83
yvantor
closed
1 year ago
2
Enforce bender directory to avoid extra checkout
#82
micprog
closed
1 year ago
0
README.md: Update to post-print citation
#81
paulsc96
closed
1 year ago
0
hw: Tune outstanding transaction count for iDMA UNBENT
#80
alex96295
closed
1 year ago
0
Silence `addr_decode` units in AXI RT
#79
thommythomaso
closed
1 year ago
1
Add a *Configuration Printer*
#78
thommythomaso
opened
1 year ago
0
treewide: Update AXI-RT, extend tests
#77
thommythomaso
closed
1 year ago
0
Bender.yml: Update `irq_router` to latest release
#76
alex96295
closed
1 year ago
0
hw: Allow for custom AXI user error bits
#75
micprog
closed
1 year ago
0
treewide: Add LLC partitioning capability
#74
DiyouS
opened
1 year ago
3
hw: Add native iDMA 2D capabilities, tune interconnect
#73
thommythomaso
closed
1 year ago
1
Update publication reference once available
#72
paulsc96
closed
1 year ago
1
hw: Fix AMO user IDs for cores
#71
paulsc96
closed
1 year ago
0
hw: Fix signal name for VGA bus error interrupts
#70
alex96295
closed
1 year ago
0
hw: Simplify UNBENT integration, some cleanup
#69
paulsc96
closed
1 year ago
0
hw: Add UNBENT bus error unit
#68
micprog
closed
1 year ago
0
tb: Defer sim termination until UART transfer is complete
#67
niwis
closed
1 year ago
0
cheshire.mk: Cache dependency paths
#66
niwis
closed
1 year ago
1
hw: Bump CVA6 to `pulp-v0.4.3`
#65
niwis
closed
1 year ago
0
hw: Expose `NumExtIntrSyncs` as design parameter
#64
alex96295
closed
1 year ago
0
hw: Update AXI RT to latest release
#63
thommythomaso
closed
1 year ago
0
hw: Add improved `axi_to_reg` adapter
#62
thommythomaso
closed
1 year ago
0
Investigate possible ZSBL performance regression
#61
niwis
opened
1 year ago
0
deps: Bump CVA6 to `pulp-v0.4.1`
#60
niwis
closed
1 year ago
0
deps: Bump `axi_riscv_atomics` to v0.8.1
#59
niwis
closed
1 year ago
0
hw: Add SMP support to boot ROM
#58
niwis
closed
1 year ago
0
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