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pulp-platform
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pulpino
An open-source microcontroller system based on RISC-V
http://www.pulp-platform.org
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Improving Modelsim Simulation Performance of Pulpino
#309
alperenbolat0
opened
5 years ago
3
fpga build fails; missing tcl files.
#308
suhasskrishanmurthy
closed
5 years ago
0
cant find some header files for FreeRtos Port
#307
suhasskrishanmurthy
closed
5 years ago
0
dead links to datasheet
#306
sebastien-riou
opened
5 years ago
0
Synthesis failed on Vivado 2016.4 due to following errors.
#305
hbhangale3
opened
5 years ago
2
error when running update-ips.py
#304
nglphucvinh
closed
5 years ago
13
error: -march=IMXpulpv2: ISA string must begin with rv32 or rv64
#303
YuaniLee
opened
5 years ago
1
Pulpino using an outdated branch of IPApproX
#302
noytzach
opened
5 years ago
0
How to do post-synthesis simulation of PULPino after generating netlist using DC
#301
kingweio
opened
5 years ago
0
Assertion Error QuestaSim
#300
SupraQuest
closed
5 years ago
1
clock problem when writing sdc file in order to synthesize PULPino
#299
kingweio
opened
5 years ago
0
problem with getting the correct bit pf Branch taken
#298
Sapir19
opened
5 years ago
0
problem when generating boot rom using boot_code.sv
#297
kingweio
opened
5 years ago
0
make helloworld error
#296
Mehrdad6991
opened
5 years ago
1
An error occurred while executing "make helloworld.vsim"
#295
kingweio
opened
5 years ago
1
datasheet not buildable because doc/datasheet/figures/pulpino_block.eps is missing
#294
stefanct
closed
5 years ago
1
Post-Synthesis simulation
#293
sofchet
opened
5 years ago
1
Problem while running "cmake_configure.riscv.gcc.sh" file
#292
Mehrdad6991
closed
5 years ago
3
The debug method of pulpino can support openocd?
#291
aorisa
closed
5 years ago
2
Write and read to a specific memory address
#290
ludblom
closed
5 years ago
0
What is the clock frequency of riscy core on zedboard?
#289
jurevreca12
opened
5 years ago
3
Post-synthesis simulation fails due to missing run_spi_ps.tcl
#288
stefanct
opened
5 years ago
1
compilation code size is too BIG !
#287
jeffcjlin
closed
5 years ago
1
Performance counter counts functions
#286
Liyang131313
opened
5 years ago
1
Fetch
#285
Liyang131313
opened
5 years ago
0
riscv objdump
#284
Liyang131313
opened
5 years ago
1
Does the FFT is optimized with the proposed hardware extension
#283
tangshibin
opened
5 years ago
1
Unable to open file `riscv_defines.pvk' Synthesize dc_compiler error
#282
sofchet
opened
5 years ago
2
Unable to use the cmake_configure.riscv.gcc.sh to build a program, output "is not able to compile a simple test program."
#281
ludblom
opened
5 years ago
14
Some fixes for fpga/
#280
stefanct
closed
5 years ago
16
Xilinx (Linux) SDK outdated
#279
stefanct
closed
5 years ago
1
Where can the "ETH gcc compiler"be found ?
#278
ogheri
closed
5 years ago
5
many regression tests failed
#277
nvlinh87
opened
5 years ago
2
bench
#276
Liyang131313
opened
5 years ago
0
Fix archlinux build (python2 and ips script)
#275
byllgrim
opened
5 years ago
1
pulp-riscv-gnu-toolchain build failed
#274
nvlinh87
closed
5 years ago
2
Can Data RAM be executed?
#273
Liyang131313
opened
5 years ago
0
A mistake in the document ???
#272
hyf6661669
closed
5 years ago
3
Why performance counters don’t start counting right away
#271
Liyang131313
opened
5 years ago
0
FPGA Compile in Vivado 2018.3
#270
xjiang3
opened
5 years ago
19
Add hardware counter
#269
sofchet
opened
5 years ago
3
Extend Data Memory
#268
StefanoSord
opened
5 years ago
1
Use the Pmod ports of the Zyboard
#267
sofchet
closed
5 years ago
4
FPGA: read a digital signal over the GPIOs
#266
sofchet
opened
5 years ago
0
Attach debugger to check code
#265
yehiafarouk
opened
5 years ago
0
Modelsim error:error loading design
#264
wooolf0455
closed
5 years ago
5
Can’t send over Uart
#263
yehiafarouk
opened
5 years ago
5
A question about "riscv_controller.sv" of the 4-stage core ri5cy
#262
hyf6661669
closed
5 years ago
0
Clearing interrupt pending flag in software?
#261
barrydebruin
opened
5 years ago
0
use the performance counter
#260
Liyang131313
opened
5 years ago
9
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