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pulp-platform
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pulpino
An open-source microcontroller system based on RISC-V
http://www.pulp-platform.org
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UART LSR[5] is not HIGH, INFINITE LOOP
#359
ghost
closed
4 years ago
0
APB 1 cycle transfer
#358
damnsavage
opened
4 years ago
0
cc1: error: bad value (‘IMXpulpv2’) for ‘-march=’ switch issue
#357
s002wjh
opened
4 years ago
0
Memory extention to 64kb
#356
gayiremre
opened
4 years ago
0
Error while running helloworld
#355
tresafebina
opened
4 years ago
0
boot rom
#354
s002wjh
opened
4 years ago
0
What is the Modelsim version required for simulation?
#353
Houlx
closed
4 years ago
0
Problem with editing files in ips folder
#352
vedanjalip
closed
4 years ago
0
Global interrup enable
#351
Ankasysemre
opened
4 years ago
0
Instruction Memory extention
#350
Ankasysemre
closed
4 years ago
1
l2
#349
Ankasysemre
closed
4 years ago
1
Problem running cmake_configure.riscv.gcc.sh
#348
baraujo3007
opened
4 years ago
0
update-ips.py command doesn't work
#347
baraujo3007
closed
4 years ago
4
> generate-scripts.py problem
#346
dig-lett
opened
4 years ago
1
strange problem when doing post-synthesis simulation
#345
65nmCMOS
closed
4 years ago
10
pulpino floating point unit
#344
Ankasysemre
closed
4 years ago
4
Illegal Instruction (core 0) at PC 0x00000084
#343
Jaina-96
opened
4 years ago
2
Cannot find module definition for L2_MB_INTERCO
#342
pgraykowski
opened
4 years ago
1
What is the mean of cmd and addr in spi_setup_cmd_addr()?
#341
holdmeplease
closed
4 years ago
1
Pulpino debuging using spi
#340
ali-zeinolabedin
opened
4 years ago
0
obtaining performance parameter
#339
pallaviboreddy
opened
4 years ago
0
cmsis-dsp software examples
#338
sunil3690
opened
4 years ago
0
signal
#337
kingweio
closed
4 years ago
0
hello_world: unrecognised emulation mode: elflriscv
#336
JunningWu
closed
4 years ago
2
pulpino fpga
#335
erihsu
closed
4 years ago
0
Where is the memory controller?
#334
shjdzc12
opened
4 years ago
0
configuring applications targated to ri5cy core in FPGA
#333
sunil3690
opened
4 years ago
0
booting zedboard using pulpino platform
#332
sunil3690
opened
5 years ago
1
How to run a test using Verilator
#331
me-sachinsingh
opened
5 years ago
1
UART issue with clock divider in sv code
#330
caifuxi
opened
5 years ago
0
How can I modify the link.common.ld if I change RAM's size?
#329
shjdzc12
opened
5 years ago
1
How can i understand the flow of the pulpino platform?
#328
madhavasahu-sevya
opened
5 years ago
0
Integrating PULPINO with NVIDIA Deep Learning Accelerator(NVDLA)
#327
fscoiety
opened
5 years ago
0
Running application on pulpino (Vivado webpack 2019.1) zynq fpga board
#326
sunil3690
closed
5 years ago
9
Synthesis and run pulpino on Zedboard or Zybo board
#325
sunil3690
closed
5 years ago
2
Running fpga application(led_demo) c code using ri5cy-gnu-toolchain.
#324
sunil3690
closed
5 years ago
6
Memory Error
#323
Ankasysemre
opened
5 years ago
2
Two problems about boot_code.sv
#322
shjdzc12
opened
5 years ago
1
Warning: pulpino_0: Component type pulpino is not in the library
#321
ViruKM
opened
5 years ago
0
Pulpino Synthesis
#320
aabimbar
opened
5 years ago
1
Thanks I solved. Now I have an other problem I've tried to do make vcompile and I obtained this:
#319
sunil3690
closed
5 years ago
0
pulpino
#318
sunil3690
opened
5 years ago
0
coremark on pulpino only get 0.6 CoreMark/MHz. Is this normal?
#317
gljiang
closed
5 years ago
0
doc: spi: SPILEN register figure
#316
rafzi
opened
5 years ago
0
doc: spi: STATUS register incomplete
#315
rafzi
opened
5 years ago
0
i want to run freeRtos on qemu with pulpino architecture
#314
suhasskrishanmurthy
opened
5 years ago
0
Problem about how to set compiler's path
#313
shjdzc12
opened
5 years ago
0
vsim freetype library error
#312
tfiorucci
opened
5 years ago
1
Update qprintf.c
#311
13163223717
opened
5 years ago
0
cant build freertos application
#310
suhasskrishanmurthy
closed
5 years ago
0
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