riscv riscv-isa-manual issues

riscv / riscv-isa-manual

RISC-V Instruction Set Manual

https://riscv.org/

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issues

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Does riscv allow vector load/store access the same device address multiple times?

#1741 AlexGJL opened 17 hours ago
2
Suggest parallelism between scounteren and mcounteren behavior

#1740 davidharrishmc closed 23 hours ago
2
Suggest removing outdated reference to user-mode interrupts

#1739 davidharrishmc closed 1 day ago
2
Remove outdated statement that Sscofpmf is written as a diff

#1737 Timmmm closed 4 hours ago
0
Vestigial sentence about future Sscofpmf extension

#1736 Timmmm closed 3 days ago
1
Can it support misaligned memory access when PBMT=NC?

#1735 Maxpicca-Li closed 1 day ago
4
instret, cycle, time outside of Zicntr (and hpmpcounterN outside Zihpm)

#1734 dhower-qc opened 4 days ago
10
[RVWMO Explanatory] Fix the figure used to illustrate atomicity axiom rule

#1733 diantaowang closed 5 days ago
0
Sscofpmf spec says it is written as a diff

#1732 Timmmm closed 4 hours ago
1
Question and Bug about "Atomicity Axiom Rule" in RVWMO Explanatory Material, Version 0.1

#1731 diantaowang closed 5 days ago
1
In the description of the Smcntrpmf extension in privilege 1.13, it states that exceptional instructions are not considered to retire, but in the privilege description of the minstret register, only ECALL and EBREAK do not increment it.

#1730 Mei-x-l closed 1 week ago
5
[CFI-zicfiss] updating pseudocode in ssamoswap unpriv

#1729 kacouane opened 1 week ago
7
Specify what imprecise traps are

#1728 Timmmm opened 1 week ago
10
Question about an implemention with Ssstateen without Smstateen

#1727 viktoryou closed 1 week ago
1
Conflicting exception types caused by misaligned AMO instructions.

#1726 jillleon007 opened 1 week ago
8
Bus-error clarification

#1725 oolegoon opened 1 week ago
2
docker: mount source and resources as read-only

#1724 arichardson closed 1 week ago
0
How to decide the memory attribute when PBMT=NC & PMA=IO ?

#1723 rock-ifly opened 1 week ago
1
Explain `sscratch` is only swapped by software

#1722 workingjubilee closed 1 week ago
1
How to understand this sentence in the PM spec--"Alternatively, an implementation may choose to "waste" TLB capacity by having up to 4 duplicate entries for each page."

#1721 chara811 opened 2 weeks ago
1
When PMLEN=16 and hgatp=sv48x4, Is GPA[49:48] =2b00?

#1720 chara811 opened 2 weeks ago
1
Can index-ordered and index-unordered VL*/VS* instructions be used to access device address space?

#1719 Steven-Li-Xiaogang opened 2 weeks ago
1
Sail Manual link is 404

#1718 ha0lyu opened 2 weeks ago
1
Understanding hypervisor extension

#1717 yf13 closed 2 weeks ago
1
Minor style fix for packh description

#1716 Peter-Herrmann closed 2 weeks ago
1
Reason for vstart≥vl requiring undisturbed tail elements even with `ta` vtype

#1715 dzaima opened 2 weeks ago
1
Add vector CSRs to CSR table

#1714 aswaterman closed 2 weeks ago
0
Confusion about "CoRR" (Coherence for Read-Read pairs) in RVWMO.

#1713 diantaowang closed 2 weeks ago
2
Add the Missing Vector CSR in listing table

#1712 MrVyM closed 2 weeks ago
0
Specify misa.M behaviour with Zmmul

#1711 Timmmm opened 2 weeks ago
3
Clarify note that compilers may need to change vtype for vmv<nr>r.v

#1710 lukel97 closed 3 weeks ago
0
Wonder why `vmvnr.v` depends on vtype

#1709 huxuan0307 closed 3 weeks ago
4
standardize "extension" suffix on extensions in priv preface

#1708 aswaterman closed 3 weeks ago
0
Add Ssqosid to extensions table in preface

#1707 ved-rivos closed 3 weeks ago
1
Move Machine/Supervisor to v1.14-draft

#1706 aswaterman closed 3 weeks ago
0
Integrated Ssqosid extension

#1705 ved-rivos closed 3 weeks ago
4
When satp =bare, can we configure vsatp and hgatp !=bare for two-stage address translation ?

#1704 chara811 closed 3 weeks ago
3
"In a two-stage address translation, is it possible to configure VSatp as sv39 and hgatp as sv48, or VSatp as sv48 and hgatp as sv39?

#1703 chara811 opened 3 weeks ago
1
When the PM feature is enabled, can PMLEN be set to 7 in sv48 mode?

#1702 chara811 opened 3 weeks ago
4
Please extend the explanation on slideup/slidedown

#1701 lu-zero opened 3 weeks ago
0
Fix NOTE about ARM FMA mnemonics

#1700 aswaterman closed 4 weeks ago
0
What are the sources of memory attributes under different translation mechanisms?

#1699 chara811 opened 4 weeks ago
4
Fix the Missing Vector CSR in listing table

#1698 MrVyM closed 2 weeks ago
0
Fix list of vector crypto extensions that require SEW=64

#1697 ebiggers opened 1 month ago
1
Improve table: Compressed instruction formats

#1696 cousteaulecommandant closed 4 weeks ago
0
why are the hstatus.VTSR/VTVM and VTW permission check different?

#1695 yinhanquan opened 1 month ago
0
Fix for issue 1693 (HSLEN should be HSXLEN)

#1694 james-ball-qualcomm closed 1 month ago
0
Hypervisor chapter uses term HSLEN but I think it means HSXLEN

#1693 james-ball-qualcomm opened 1 month ago
2
Vector Indexed Instructions' order is memory Consistency rule or just elements' order whose address overlap?

#1692 AlexGJL closed 1 month ago
8
Consider changing the bit-order in a byte from right-to-left to left-to-right

#1691 gintominto5329 closed 1 month ago
7