sheldonucr ucr-eecs168-lab issues

sheldonucr / ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside

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issues

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Lab 2 LVS error

#100 adela025 closed 4 years ago
0
I had issue on simulation step I still cant figure out

#99 gawad357 closed 4 years ago
0
Cant start cdesigner

#98 GauravAdlakha16570 opened 4 years ago
1
LVS Debugger claiming layout has 3 nets when theres only 2 connections

#97 arvelreeves opened 4 years ago
0
Crashed while running LVS test, now cannot run test

#96 arvelreeves closed 4 years ago
0
Where is the room for the lab demo?

#95 raajraj opened 4 years ago
1
Tomorrow office hours

#94 ahernandez25 opened 4 years ago
2
same issue as before

#93 gawad357 closed 4 years ago
0
How to setup DC simulation with multiple inputs for NAND gate testbench

#92 ryanmeoni closed 4 years ago
1
"The Object is Invalid" when i run Verification -> DRC -> Setup and Run

#91 iperson98 opened 4 years ago
0
Lab 2 Type Error

#90 tsandytsan opened 4 years ago
2
VPN crashed while trying to work on lab, now cannot edit the layout file as it's read only

#89 arvelreeves opened 4 years ago
4
Lab 2 DRC Issue

#88 adela025 closed 4 years ago
1
NAND test bench parameters

#87 MengEnLu opened 4 years ago
0
error opening cdesigner&

#86 gawad357 opened 4 years ago
6
X server connection

#85 ejredondo closed 4 years ago
0
How to submit waveforms/schematics for lab1?

#84 ryanmeoni opened 4 years ago
1
LAB 1 Cannot Save Modified Inverter Symbol

#83 MengEnLu closed 4 years ago
1
Do we need to come to lab for the pre-lab if we completed it on our own?

#82 ryanmeoni opened 4 years ago
1
Final Exam Inquiry

#81 adrianmoo2 closed 5 years ago
1
Lab 4 Checkoff

#80 joshacola closed 5 years ago
1
[Lab04] Error with gui_start

#79 adrianmoo2 opened 5 years ago
7
Lab 4 rotated 4bit adder

#78 dannyesaid opened 5 years ago
1
Lab 4 correction

#77 geoffreynguyen011 opened 5 years ago
5
[LAB03] Stick Diagram Clarification

#76 adrianmoo2 opened 5 years ago
4
Waveform Issue

#75 Y0ungMun opened 5 years ago
3
Lab 3 Checkoffs

#74 Tsukuyomiiii closed 5 years ago
1
Lab 3 Checkoff

#73 exoticmoose closed 5 years ago
0
Lab 3 Checkoff

#72 codyiskhuu closed 5 years ago
1
Lab #3 LVS Error (text_net:text_short)

#71 adrianmoo2 opened 5 years ago
9
Lab3 convergence aid

#70 dannyesaid opened 5 years ago
4
Office hours

#69 Tsukuyomiiii closed 5 years ago
1
Do we connect COUT back into CIN?

#68 danieltan1517 opened 5 years ago
1
4 bit adder: simulation result with parasitic extraction

#67 jborjaj closed 5 years ago
1
Connecting layout M1 to pins without bus

#66 dannyesaid opened 5 years ago
3
Connecting poly with M2

#65 jborjaj opened 5 years ago
1
Lab checkoff question

#64 Tsukuyomiiii closed 5 years ago
1
Bizarre Error

#63 danieltan1517 closed 5 years ago
1
Lab drop in

#62 dannyesaid closed 5 years ago
1
LPE Error with 1-bit Full Adder Circuit

#61 spick002 opened 5 years ago
1
LVS: Text Short

#60 spick002 closed 5 years ago
1
Lab 2 NAND gate late demo

#59 adrianmoo2 closed 5 years ago
5
No voltage shown in custom desing consol Lab3 Full adder

#58 jborjaj closed 5 years ago
7
Merge pull request #1 from sheldonucr/master

#57 fengcda closed 5 years ago
0
Merge pull request #2 from sheldonucr/master

#56 fengcda closed 5 years ago
0
Demoing for lab 3

#55 geoffreynguyen011 closed 5 years ago
1
Lab 2 Demo Appointment

#54 Y0ungMun closed 5 years ago
3
Appointment for Lab 2 demo

#53 jpedr010 closed 5 years ago
1
regarding running the DRC

#52 cybertron97 opened 5 years ago
4
lab2 demo/checkoff appointment

#51 kazaller closed 5 years ago
2

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