sifive fpga-shells issues

sifive / fpga-shells

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bscan.scala jtag_tms

#171 HaogeL opened 2 years ago
0
Virtex

#170 Rudi472 opened 2 years ago
0
fix for chipsalliance/rocket-chip#2925

#169 sequencer opened 2 years ago
0
remove objectmodule

#168 sequencer opened 2 years ago
0
FPGA Prototyping Error Caused by Vivado Tcl Interpreter: fpga-shells/xilinx/common/tcl/prologue.tcl

#167 zslwyuan opened 2 years ago
1
fixed parameter of IBUF_DELAY_VALUE type error

#166 KingFrige opened 2 years ago
0
VCU118 Edge PCIe doesn't seem functional

#165 michael-etzkorn closed 2 years ago
1
Add support for Xilinx Virtex UltraScale FPGA VCU108 board

#164 ariusewy opened 3 years ago
0
"SPI Flash not functional"

#163 michael-etzkorn opened 3 years ago
4
fix critical warning for Vivado

#162 sequencer opened 3 years ago
2
add inline blackbox to PowerOnResetFPGAOnly.

#161 sequencer opened 3 years ago
0
Add support for Xilinx Virtex-7 FPGA VC709 board

#160 mbs0221 opened 3 years ago
0
Add support for Digilent Genesys 2 board

#159 yqszxx opened 3 years ago
1
Add Xilinx IBUF_LOW_POWER property

#158 abejgonzalez closed 3 years ago
2
bump sifive-blocks

#157 zizztux closed 3 years ago
0
DDR controllers: do not use deprecated stripBits parameter of TLToAXI4

#156 hcook closed 3 years ago
0
Add Xilinx drive strength property

#155 abejgonzalez closed 3 years ago
0
Add TRNG top IO(PAD) for entropy characterisation

#154 albavince closed 3 years ago
2
Add por gen overlay

#153 KowshikSiFive closed 4 years ago
0
PMOD2 and PCIe key on vcu118 new shell

#152 Jacka1201 closed 4 years ago
1
JSON support to generate scala module

#151 sidharth94 closed 4 years ago
2
fix arty LEDs

#150 erikdanie closed 4 years ago
0
SPIOverlay: Fix makeSink'd scope to sinkScope

#149 rmac-sifive closed 4 years ago
0
SDIO Overlay: Refactor to be more useful for generic SPI IO creation

#148 rmac-sifive closed 4 years ago
0
Overlay refactor

#147 asmitde closed 1 year ago
1
Critical Warning on addIOB

#146 sequencer opened 4 years ago
0
add clock divider support

#145 sequencer closed 4 years ago
1
refactor tcl code that wasn't executing correctly

#144 erikdanie closed 4 years ago
0
inline PowerOnResetFPGAOnly

#143 sequencer closed 3 years ago
0
CI: add a scala compilation check

#142 terpstra closed 4 years ago
0
SDIO: chisel3 <> can't decide connection direction

#141 terpstra closed 4 years ago
0
fix bscan again

#140 sequencer closed 4 years ago
0
xdma: support BARs with physical address != PCIe address

#139 terpstra closed 4 years ago
0
Add padPlace: LazyScope value

#138 kimdh727 closed 4 years ago
1
wake: add variable for package location

#137 mmjconolly closed 4 years ago
0
Locate IO srst_n to proper pin on LCD connector

#136 ernie-sifive closed 4 years ago
1
add tcl script to only do synth.tcl

#135 erikdanie closed 4 years ago
0
optional th, designKeyWithTestHarness

#134 erikdanie closed 4 years ago
1
bug fix for #103

#133 sequencer closed 4 years ago
1
GPIO: Rename ShellGPIOPortIO width param

#132 rmac-sifive closed 4 years ago
0
SiFive Intel FPGA Direction Request

#131 jtarango opened 4 years ago
2
add pin constraint for srst_n on vc707

#130 erikdanie closed 4 years ago
1
move cjtag to vcu118 fmc

#129 erikdanie closed 4 years ago
0
cjtag on vcu118

#128 erikdanie closed 4 years ago
0
separate baremetal shell and linux shell

#127 erikdanie closed 4 years ago
1
VCU118: JTAG conflicts with SDIO for the PMOD

#126 terpstra closed 4 years ago
1
Chisel compile warning: deprecated IntSyncCrossingSink

#125 ingallsj closed 4 years ago
0
Ethernet on VC707 or VCU118

#124 jctullos closed 4 years ago
2
ethernet: clarify which kind of resets are used

#123 terpstra closed 4 years ago
0
Restore s_rst_n connection

#122 daveparry closed 4 years ago
0