sinara-hw Sayma_RTM issues

sinara-hw / Sayma_RTM

RTM board with 8-channel GS/s DAC, 125MS/s ADC and flexible clock circuit

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issues

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EN_PWR_HMC830 is shorted to ground

#72 marmeladapk closed 5 years ago
1
Capacitor between DXP and DXN

#71 marmeladapk closed 5 years ago
1
Missing files

#70 marmeladapk closed 5 years ago
1
N12V0A/P12V0A diodes?

#69 hartytp closed 5 years ago
7
RTM FPGA needs to see clock before HMC chips

#68 sbourdeauducq closed 5 years ago
9
Two sources of P3V3_CLK power

#67 WeiDaZhang closed 5 years ago
1
HMC830 loop filter R4

#66 hartytp closed 5 years ago
0
CDR_CLEAN3 connects to CDR_CLEAN0

#65 hartytp closed 5 years ago
0
check HMC830 connections match dev kit

#64 hartytp closed 5 years ago
3
replace UFLs with MMCX?

#63 hartytp closed 5 years ago
3
WR connections

#62 hartytp closed 5 years ago
1
DNP R386

#61 hartytp closed 5 years ago
0
LDO Vset bypass

#60 hartytp closed 5 years ago
4
dnp active loop filter

#59 hartytp closed 5 years ago
1
dac channels cross-wired

#58 hartytp closed 5 years ago
1
exar

#55 hartytp closed 5 years ago
2
DAC JESD

#54 hartytp closed 5 years ago
2
GPIO/debug port

#51 sbourdeauducq closed 5 years ago
1
HMC830 active loop filter

#49 hartytp closed 5 years ago
13
drive AFE REF clock inputs from HMC7043 and not from upstream ADCLK948

#48 jordens closed 5 years ago
6
I2C switch reset

#47 jordens closed 5 years ago
1
layout fixes

#46 gkasprow closed 5 years ago
1
spare GTP channels

#45 sbourdeauducq closed 5 years ago
17
swapping FPGA banks 14 and 34

#44 gkasprow closed 5 years ago
2
observing DAC output for debugging

#43 sbourdeauducq closed 5 years ago
9
M2_0: add 0R

#42 jordens closed 5 years ago
1
consider increasing i2c pullup resistances

#41 jordens closed 5 years ago
2
Slave SATA label is unreadable

#40 sbourdeauducq closed 5 years ago
1
index DACs at 0

#39 sbourdeauducq closed 5 years ago
2
use differential uFL for REF clock output

#38 sbourdeauducq closed 5 years ago
1
resistive divider for 50MHz oscillator

#37 sbourdeauducq closed 5 years ago
4
bank 34 does not have voltage indication on schematics

#36 sbourdeauducq closed 5 years ago
4
more SYSREFs to FPGA

#35 sbourdeauducq closed 5 years ago
7
use only one Si5324 output

#34 sbourdeauducq closed 5 years ago
4
scrap TI DCXO

#33 hartytp closed 5 years ago
1
Sayma RTMv2 design changes

#32 gkasprow closed 5 years ago
1
Sayma RTMv2 mechanics

#31 gkasprow closed 5 years ago
3
DAC clock PLL

#30 hartytp closed 5 years ago
7
Sayma v2.0 clocking/synchronisation write up

#29 hartytp closed 5 years ago
5
ADF4356 testing writeup

#28 hartytp closed 5 years ago
19
CDR_CLK_CLEAN1 connection

#27 atcher0 closed 5 years ago
1
DAC0 CLK/SYSREF connection

#26 atcher0 closed 5 years ago
1
FPGA pinout

#25 jordens closed 5 years ago
9
FPGA_CFG_DIN

#24 tprzywoz closed 5 years ago
3
RTM_FPGA_GTP_CLK _P and _N lines

#23 tprzywoz closed 5 years ago
0
HMC830

#22 hartytp closed 5 years ago
5
adf PLL review

#21 hartytp closed 5 years ago
10
clock probe points

#20 hartytp closed 5 years ago
1
remove IC26

#19 hartytp closed 5 years ago
1
remove screening cans

#18 hartytp closed 5 years ago
2

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