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AnTiQ
A hardware priority queue with constant response time written in SystemVerilog.
Apache License 2.0
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Fix FPGA synthesis
#7
ANurmi
closed
3 months ago
0
`make build` to run synthesis is failed.
#6
zflcs
closed
3 months ago
2
fix rand_id
#5
ANurmi
closed
8 months ago
0
[TB] Fix tb
#4
ANurmi
closed
8 months ago
0
[RTL, TB] bug fixes & tb improvements
#3
ANurmi
closed
9 months ago
0
[RTL, TB]
#2
ANurmi
closed
9 months ago
0
[RTL] FSM fixes
#1
ANurmi
closed
9 months ago
0