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stanford-ppl
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spatial
Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
https://spatial.stanford.edu
MIT License
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One gatherBuffer in Fringe can cause another one to hang
#118
mattfel1
closed
6 years ago
2
Add dot backend
#117
yaqiz01
closed
6 years ago
0
DenseTransfer Crashes on Aliases3Dto2DTransfers
#116
mattfel1
closed
6 years ago
1
Outsource Verilog Arithmetics to Vivado
#115
mattfel1
opened
6 years ago
0
TransientCleanup Crash In Some Combination of SimpleStruct + Switch
#114
mattfel1
closed
6 years ago
2
Properly Forward Constants Through BlackBoxes
#113
mattfel1
closed
6 years ago
1
Tweak Cost Metric for MemoryConfigurer
#112
mattfel1
closed
5 years ago
1
Retiming of Action and NextState in StateMachine
#111
mattfel1
closed
6 years ago
1
Saturating and Unbiased Rounding Conversions
#110
mattfel1
closed
6 years ago
1
Connecting Buffer Control Logic for Memory with Accesses across Parallel but in Lockstep
#109
mattfel1
closed
6 years ago
0
Merging Instances When Accesses Come from Different Unroll Paths
#108
mattfel1
closed
6 years ago
1
Add Support for Floats for --synth
#107
mattfel1
opened
6 years ago
0
Simplify and Correct Backpressure Logic
#106
mattfel1
closed
6 years ago
0
Clean Logic for Stream Controllers
#105
mattfel1
closed
6 years ago
1
Look-Through RegReads in Access Analyzer
#104
mattfel1
opened
6 years ago
7
LineBuffers
#103
mattfel1
closed
6 years ago
2
Bank Conflicts Due to Non-Lockstep Accesses
#102
mattfel1
closed
6 years ago
2
bin/spatial Unexpectedly Doesn't Work
#101
mattfel1
closed
6 years ago
0
Faulty Broadcasting Due to False-Positive on Lockstep Check
#100
mattfel1
closed
6 years ago
2
Loop Perfecter
#99
mattfel1
opened
6 years ago
4
Conflicting Port Connections
#98
mattfel1
opened
6 years ago
3
Vanishing Mux
#97
mattfel1
closed
6 years ago
1
Mysterious mux deletion
#96
dkoeplin
opened
6 years ago
1
Broadcast issue with SingleLayerConv_RCIO
#95
dkoeplin
closed
6 years ago
1
Double Connections To Port for RegRead
#94
mattfel1
closed
6 years ago
1
[WIP] Clean up old/unused source files, tests, and resources
#93
dkoeplin
closed
6 years ago
0
muxSize in Port is incorrect and unused
#92
dkoeplin
closed
6 years ago
2
Synth Out of Memory
#91
ZhijieWang
closed
6 years ago
2
Port Info Conflicts On RegRead When Unrolling Inside Of Switch
#90
mattfel1
closed
6 years ago
2
ScalaGen emitControlObject Mistake
#89
mattfel1
closed
6 years ago
2
Periodically revise control schedule based on constraints
#88
dkoeplin
opened
6 years ago
0
Make RegReads Used to Set Up Controllers Buffer Correctly
#87
mattfel1
closed
6 years ago
1
Buffer Recompute After Unrolling
#86
mattfel1
closed
6 years ago
0
Fix buffering logic for more exotic cases
#85
mattfel1
opened
6 years ago
1
sim and synth mismatch
#84
shadjis
closed
6 years ago
2
Inner SwitchCase Body Latency Not Set
#83
shadjis
closed
6 years ago
2
Hierarchical Banking - Bank Calculation Wrong
#82
shadjis
closed
6 years ago
2
[WIP] Broadcast support
#81
dkoeplin
closed
6 years ago
0
Issue75 excessive wires
#80
mattfel1
closed
6 years ago
3
Argon gotcha: Subclassing metadata types has weird behavior
#79
dkoeplin
opened
6 years ago
0
Add mismatched dimension loading/storing
#78
dkoeplin
opened
6 years ago
2
Pipeline depth expected?
#77
shadjis
opened
6 years ago
2
Update Documentation / Getting Started Tutorial
#76
ZhijieWang
closed
6 years ago
2
Cut Back on Excessive Wires
#75
shadjis
closed
6 years ago
7
Nodes Not Duplicated When Reused In Certain Ways
#74
mattfel1
closed
6 years ago
1
par not speeding up
#73
shadjis
closed
6 years ago
6
negative array crash
#72
shadjis
closed
6 years ago
2
[WIP] iteration difference detection
#71
mattfel1
closed
6 years ago
1
[WIP] Specialize accumulators
#70
dkoeplin
closed
6 years ago
2
FIFO Banking Analysis Seems Broken Suddenly
#69
mattfel1
closed
6 years ago
1
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