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stanford-ppl
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spatial
Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
https://spatial.stanford.edu
MIT License
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Warning for Const out of range Missing
#168
mattfel1
opened
5 years ago
2
Potential asBits issue in VCS
#167
mattfel1
opened
5 years ago
0
Fork Inside ForkJoin With Pipe Insertion (Reprise)
#166
mattfel1
closed
5 years ago
3
Unset value (for --sim)
#165
mattfel1
opened
5 years ago
1
Bias for scatter/gather API
#164
mattfel1
closed
5 years ago
1
Add/Scrub Instrumentation for Understanding DRAM Bottlenecks
#163
mattfel1
closed
5 years ago
1
Mysterious ISL Issue
#162
mattfel1
closed
5 years ago
3
Start using Chisel's FixedPoint
#161
mattfel1
opened
5 years ago
0
Add Loop break
#160
mattfel1
closed
5 years ago
1
Add Syntax for Packing/Concatenating raw bits into new number
#159
mattfel1
closed
5 years ago
2
Fill in Spectrum between full cross-bar access and directly banked access
#158
mattfel1
closed
5 years ago
1
Issue155 memreduce
#157
mattfel1
closed
6 years ago
0
Unify and Enhance dot and treegen
#156
mattfel1
closed
5 years ago
1
Unit Pipe Substitution for Reduce Stage in OpMemReduce Trips Unroller
#155
mattfel1
closed
5 years ago
1
Better Doc Scrubber
#154
mattfel1
closed
5 years ago
1
Frustrating Systolish Behavior
#153
mattfel1
closed
6 years ago
1
Pipeline of Parallels vs Parallel of Pipelines for Unrolling
#152
mattfel1
closed
5 years ago
3
Auto Schedule Controllers in Parallel if no dependencies
#151
mattfel1
closed
5 years ago
2
Bring back LUT.fromFile
#150
mattfel1
closed
6 years ago
1
Misc fixes
#149
mattfel1
closed
6 years ago
0
Add scala-gdocs regression option
#148
mattfel1
closed
6 years ago
1
Resource reporting
#147
pyprogrammer
closed
6 years ago
0
add scatter
#146
mattvilim
closed
6 years ago
0
implement up to 2 layer chunking for chisel and scala gen
#145
mattfel1
closed
6 years ago
0
Implement Deeper Chunking Hierarchy in Generated Code
#144
mattfel1
closed
6 years ago
2
[WIP] DSE
#143
mattfel1
closed
6 years ago
0
Shifting FixPt by Amount Bigger Than Int bits
#142
mattfel1
closed
6 years ago
1
Regular vs Broadcasting Reset
#141
mattfel1
opened
6 years ago
0
Port DSE to New Spatial!
#140
mattfel1
opened
6 years ago
0
Delay Line Type Doesn't Match Its Input Type
#139
mattfel1
closed
6 years ago
1
Host vs. Accel DRAM syntax is confusing
#138
dkoeplin
opened
6 years ago
2
Support Xilinx and Altera Simulation
#137
mattfel1
opened
6 years ago
2
Print II and Latency in html
#136
mattfel1
closed
6 years ago
1
Hierarchical Banking Being too Conservative
#135
mattfel1
closed
6 years ago
1
Refactor Generated Chisel to look like --sim backend
#134
mattfel1
closed
6 years ago
1
Sanity Check Duplication vs Time-Multiplex Rules for Readers
#133
mattfel1
opened
6 years ago
0
[WIP] Refactor chisel templates (fringe), add floating point support
#132
dkoeplin
closed
6 years ago
0
FixPt Implementations for Harder Functions
#131
mattfel1
opened
6 years ago
0
PipeInsertion Inside of Stream Controller Not Respecting Stream Scheduling
#130
mattfel1
closed
6 years ago
1
Port Arria10 SoC Target from spatial-lang
#129
mattfel1
opened
6 years ago
0
Support Arria10 PAC
#128
mattfel1
opened
6 years ago
0
Support KCU1500 Board
#127
mattfel1
closed
5 years ago
1
Support VU9P Board
#126
mattfel1
opened
6 years ago
0
Add Tutorials Specifically on How to Improve Performance
#125
mattfel1
closed
6 years ago
1
[WIP] Implementation of LineBuffers
#124
mattfel1
closed
6 years ago
0
Allow Duplication for Dephased Accesses that Cannot be Banked Together
#123
mattfel1
closed
6 years ago
1
Stricter Lockstep Check
#122
mattfel1
closed
6 years ago
1
DefiningBlk not defined outside accel and inside IfAndElse
#121
yaqiz01
closed
6 years ago
1
MAG Channel Balancer
#120
mattfel1
opened
6 years ago
0
Shrink bitwidths for indices of statically known counters
#119
mattfel1
opened
6 years ago
0
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