ttchisholm / 10g-low-latency-ethernet

10G Low Latency Ethernet
MIT License
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cocotb ethernet fpga pyuvm systemverilog xilinx

10G Low Latency Ethernet

cocotb-test

Overview

For more information, refer to my blog series for this project - Designing a Low Latency 10G Ethernet Core - Part 1 (Introduction)

This repository contains:

Repository structure:

.github/        # GitHub workflow
example/        # Example design
src/            # Ethernet core source
    hdl/            # HDL source
    ip/             # IP generation
    lib/            # Submodules
    tb/             # Testbenches

Example Design

Building the example design:

  1. Clone the slicing_crc submodule
git submodule update --init --recursive
  1. Generate GTY IP. Set the FPGA part and GTY channel in src/ip/gen_eth_10g_ip.sh and run
cd src/ip  
./gen_eth_10g_ip.sh
  1. Modify the constraints file example/constraints/example_10g_eth.xdc with appropriate pin assignments. The design requires a 100MHz clock input for initialisation and a low-jitter 156.25MHz clock for the transceivers

  2. Build the example design. Set the FPGA part again in example/build_example.sh

cd example
./build_example.sh
Vivado> all

Running the example design:

  1. Program the device in Vivado Hardware Manager
  2. Add the VIOs
  3. De-assert core_reset in hw_vio1 (u_core_reset_vio)
  4. De-assert packet_gen_reset in hw_vio3 (u_packet_control_vio)
  5. Capture on hw_ila_2 (tx_packet_ila) to observe latency