For more information, refer to my blog series for this project - Designing a Low Latency 10G Ethernet Core - Part 1 (Introduction)
This repository contains:
Repository structure:
.github/ # GitHub workflow
example/ # Example design
src/ # Ethernet core source
hdl/ # HDL source
ip/ # IP generation
lib/ # Submodules
tb/ # Testbenches
Building the example design:
git submodule update --init --recursive
cd src/ip
./gen_eth_10g_ip.sh
Modify the constraints file example/constraints/example_10g_eth.xdc with appropriate pin assignments. The design requires a 100MHz clock input for initialisation and a low-jitter 156.25MHz clock for the transceivers
Build the example design. Set the FPGA part again in example/build_example.sh
cd example
./build_example.sh
Vivado> all
Running the example design: