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constellation
A Chisel RTL generator for network-on-chip interconnects
http://constellation.readthedocs.io
BSD 3-Clause "New" or "Revised" License
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problem with compiling CONSTELLATION_STANDALONE=1 sbt "testOnly constellation.NoCTest00"
#77
SoCScholar
opened
1 day ago
1
How to run the tests in test folder
#76
pointerliu
closed
1 month ago
1
AXI4Noc AXI4EdgeParameters config
#75
qwerssss1
opened
2 months ago
0
Butterfly topology with AXI protocol
#74
qwerssss1
closed
2 months ago
0
constellation/src/main/scala/channel/Nodes.scala:4:8: object SourceInfo is not a member of package chisel3.experimental
#73
wudehua2016
closed
2 months ago
1
Connecting the AXI_MMIO Master Port in Chipyard
#72
eric900115
closed
3 months ago
0
No .v(verilog) file generated after running Chipyard-Standalone Testing
#71
danielfufu
opened
4 months ago
2
May I ask how to get the .Generator here, it reports this error.
#70
yoyo115956
opened
4 months ago
5
Chipyard-Standalone mode Raising FixedPoint Issues
#69
yoyo115956
closed
2 months ago
1
Chipyard-Standalone Testing with Config AXI4TestConfig00
#68
qwerssss1
opened
5 months ago
2
about Minimal-Standalone Testing
#67
beiming0110
opened
7 months ago
6
report error when execute Minimal-Standalone Testing
#66
TDppy
opened
8 months ago
8
Setup Issue
#65
hukangha
closed
8 months ago
2
Support inlining noc routers out of the grouped TL buses
#64
jerryz123
closed
8 months ago
0
Bump CI to 3.6.0
#63
jerryz123
opened
10 months ago
0
Update deprecated Chisel API
#62
tymcauley
closed
9 months ago
1
Remove empty parens from `fire` method calls
#61
tymcauley
closed
10 months ago
0
Max throughput of Random traffic
#60
zliu2014
opened
11 months ago
4
Remove vc_free bypass in output unit
#59
jerryz123
closed
11 months ago
0
confuse about inNodeMapping and outNodeMapping
#58
FDH21
opened
1 year ago
2
Improvements to TileLink-NoC
#57
jerryz123
closed
1 year ago
0
fix: use bitwise not instead of logical not
#56
ToruNiina
closed
1 year ago
1
connecting the cores of the SOC with TLNOC
#55
yulilicao
opened
1 year ago
0
`DiplomaticNetworkNodeMapping` fails with more than 9 cores
#54
mayyxeng
opened
1 year ago
2
How the DiplomaticNetworkNodeMapping string to decide?
#53
yulilicao
closed
1 year ago
0
No .v(verilog) file generated after running Chipyard-Standalone Testing
#52
furoge
opened
1 year ago
1
Failed: Chipyard-Standalone Testing
#51
furoge
opened
1 year ago
1
Failed: Running Minimal-Standalone Testing
#50
furoge
closed
1 year ago
2
genenarate top.v fail
#49
Kt985
closed
1 year ago
1
Support FIFO flows
#48
jerryz123
closed
1 year ago
0
Added comments to explain Mbus, Sbus, etc. shorthands
#47
JL102
closed
1 year ago
1
Question: What are the parameters in the example Butterfly config?
#46
JL102
closed
1 year ago
4
Running a Simple Evaluation
#45
ashuthosh-mr
opened
1 year ago
8
Run AXI4TestConfig02 fail in the chipyard
#44
yulilicao
closed
1 year ago
3
Is there anyway to generate seperate verilog files for each component?
#43
yinlee
closed
1 year ago
1
Add Wishbone protocol support
#42
manili
opened
1 year ago
2
May I ignore the "[error] Picked up JAVA_TOOL_OPTIONS" error?
#41
manili
closed
1 year ago
1
Error encountered while testing hierarchical topology in Chipyard 1.8.1
#40
astrohan
closed
1 year ago
11
Bump to latest rocket-chip
#39
jerryz123
closed
1 year ago
0
Run Minimal-Standalone Testing Fail
#38
CathyGong516
closed
1 year ago
7
test
#37
jerryz123
opened
1 year ago
0
Add missing netrace resource
#36
AnimeshAgrawal
closed
1 year ago
0
Run NocTestAXI403 Fail
#35
Alan-19950616
opened
1 year ago
9
Bump to scala 2.13
#34
jerryz123
closed
1 year ago
1
fix: remove EnhancedChisel3Assign in rocket-chip;
#33
SingularityKChen
closed
1 year ago
0
Export NoC Config as a JSON
#32
AnimeshAgrawal
opened
1 year ago
0
Export NoC Config as a JSON file
#31
AnimeshAgrawal
closed
1 year ago
1
Add option to generate input buffers without per-VC queues
#30
jerryz123
closed
2 years ago
0
Update Topologies.rst
#29
whutddk
closed
2 years ago
0
fix: S-interpolator for assert, assume and printf
#28
SingularityKChen
closed
1 year ago
0
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