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AMF-Placer
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
Apache License 2.0
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Can i have the original design and device file of the VCU108?
#13
BQ233
closed
8 months ago
1
Dev
#12
SivanLaai
closed
1 year ago
1
can't reach patoh-Linux-x86_64.tar.gz
#11
SivanLaai
closed
1 year ago
2
Could not find "Q_WS_WIN", "Q_WS_QWS" and "Q_WS_MAC" during the cmake
#10
tomqingo
opened
1 year ago
1
Timing-driven FPGA Placement enabled
#9
zslwyuan
closed
2 years ago
1
Extension to other Xilinx FPGA device
#8
lesliepy99
closed
2 years ago
5
Please don't hesitate to contact us if you encounter problems with our AMF-Placer
#7
zslwyuan
opened
2 years ago
0
Legalization bugs when cells in a macro are placed across clock region
#6
zslwyuan
closed
2 years ago
1
WARNING: We are integrating the timing-driven functions and it might lead to unstable problems of benchmark "OptimSoC"
#5
zslwyuan
closed
2 years ago
2
After introducing timing optimization, some half-column clock regions get legalization violation (will be solved soon)
#4
zslwyuan
closed
3 years ago
1
reorganize the architecture of the placer and make processors act like LLVM passes(TODO)
#3
zslwyuan
opened
3 years ago
1
[FIX] function under conda environment.
#2
magic3007
closed
3 years ago
0
SLR/Clock/Congestion-Aware Initial Placement
#1
zslwyuan
closed
3 years ago
0