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Hello,
I am trying to follow along with the labs and I was under the impression that this GitHub repository will have all of the necessary supporting material for the labs. There seems to be no DE1…
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hi
Why is there no script for compiling the Zybo bitstream in Vivado? I'm aware that it's possible to dynamically configure the FPGA's bin file (https://github.com/ikwzm/FPGA-SoC-Linux-Example-1-ZYBO…
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Is that an oxymoron?
Does Kvasir apply to an embedded linux implementation?
We are using an SOC that includes APUs that run an embedded linux as well as RPUs that look more like a traditional m…
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Hi,
I recently tried to build this project on a M3 Macbook Pro inside a NixOS virtual machine and it did not work.
Afterwards I tried to update the flake and the project wouldn't build on a x86-64…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Red Semi is trying to get Linux running on the Nexys Video build of the CVA soc, and th…
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I have followed the instructions in the readme so far but when it comes to loading the bitstream to the Arty A7-100 I get errors.
When I run `./make.py --board=arty --load` i get this error:
`Tr…
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Hello! Thank you for this wonderful project, Mr. Tarassov.
I wish to add a CAN peripheral. Would you recommend doing this using the provided [Vivado CANFD IP](https://www.xilinx.com/products/intel…
ahmrr updated
21 hours ago
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Can you consider to implement generic uio in your python periphery? As i see your MMIO implementation can serve the reg mapping for a /dev/uioX, only the IRQ waiting which is needed to implemented for…