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I think we should switch from Make to CMake. This would have a number of benefits:
1. We can easily make the arch part of the targets instead of a Make parameter. I.e. instead of
```
ARCH=RV32 …
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RISCV_DEBUG is never used, but could be used to determine if the emulator should be built with certain single-instruction-level debugging support. Something to think about. The emulator is considered …
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the make process is finished, and make run-emulator error shown as follow:
```
hessen@ParaComp:~/risc-v/riscv-sodor$ make run-emulator
running basedir/Makefile: make run-emulator
make -C emula…
hz0ne updated
6 months ago
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I'm running test cases randomly generated by Google's [riscv-dv](https://github.com/google/riscv-dv) on the sail-riscv c_emulator model.
It runs a few thousand instructions and then dies:
```
[23…
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I am getting following error in "make run-emulator"
verilator --cc --exe --top-module Top +define+PRINTF_COND=1 --assert --output-split 20000 --x-assign unique -I/home/farhad/Downloads/riscv-sodor…
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Sail currently sets bits C, D, E, F, M, V and X in `misa`. This is wrong as D (double float), F (float) and V (vector) are not supported. ~~Also B (bit vector) is supported and should be set~~ (remove…
rmn30 updated
2 months ago
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When attempting to compile the current version of this PR: https://github.com/riscv/sail-riscv/pull/197 I get an error when compiling the C file generated by Sail:
```
make csim
gcc -g -I /mnt/rus…
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Hy there,
I completed the git clone and RISC-V front-end install to /usr/local/
After
```
./configure --with-riscv=/usr/local
make
```
I get
```
g++ -I. -MMD -I/usr/local/share/verilat…
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### Technical Group
Applications & Tools HC
### ratification-pkg
Technical Debt
### Technical Liaison
Bill McSpadden
### Task Category
Sail
### Task Sub Category
- [ ] gcc
…
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The CI version builds OCaml emulator with a lot of warnings. The most severe of them is
````
File "riscv.ml", line 12439, characters 4-48:
12439 | Softfloat.f64_round_to_int (zrm, zv, zexact);…