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Do you think it's feasible to make a tool for valgrind to convert RV32 code to RV64 on the fly?
e.g. see `slli` or `c.slli`, pretend you saw `slliw`, etc.
It seems that if you want to simply run…
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# Official Test suite
[RISC-V Tests](https://github.com/riscv-software-src/riscv-tests)
## How to setup *Linux only*
[Prerequisites](https://github.com/riscv-collab/riscv-gnu-toolchain/blob/master/…
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Jolt can theoretically support 64-bit word sizes with relative ease. We would like to evaluate the extent to which RV64 would be more efficient than RV32 for certain programs. For example, we expect R…
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**Describe the bug**
When created 2 RiscvAtomicSimpleCPU in fs_linux --bare-metal , i want modify cpu[0].ArchISA.riscv_type="RV64" cpu[1].ArchISA.riscv_type="RV32",
It was found after tested both cp…
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LLDB requires that the full list of registers is provided.
For example, for rv32, this string is currently returned:
```rs
fn target_description_xml() -> Option
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Hi!
The unprivileged specification version 20240411 states that:
> Any AMO can be emulated by an LR/SC pair
Is this with exception of AMOCAS.D for RV32? Since:
> An SC can only pair with the m…
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## Precommit CI Run information
Logs can be found in the associated Github Actions run: https://github.com/ewlu/gcc-precommit-ci/actions/runs/10575659769
## Patch information
Applied patches: 1 -> 1
A…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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* https://github.com/riscv-collab/riscv-gnu-toolchain#installation-newliblinux-multilib
> The musl compiler (riscv64-unknown-linux-musl-) will only be able to target 64-bit systems due to limitatio…
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the RV32/64G instruction set listing chapter is a really handy summary for those of us who have to work on assemblers/disassemblers/emulators. recent versions of the spec are a great improvement in te…