verilog-hdl Search Results

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hz12opensource/libresdr #14

Programming fpga on libreSDR verilog, system verilog, HDL, V…

I want to program the PL part of ZYNQ, but I need a backup of the bitstream. Where can I get it from? If you think about it, LibreSDR is a clone of PlutoSDR, but does that mean that a project for Viva…

Max-911-gif updated 1 month ago
1
EPFL-LAP/dynamatic #171

[VHDL/Backend] Incompatible signal types for 1-bit address

**Commit:** bdfc973d4ed46ff2b3ac5765c2063543b6425a9a To reproduce the issue: ``` dynamatic> set-dynamatic-path ./dynamatic; set-src ./dynamatic/integration-test/admm/admm.c; set-clock-perio…

Jiahui17 updated 1 week ago
2
sourcegraph/sourcegraph-public-snapshot #28259

Support syntax highlighting for HDL Languages (Verilog and V…

#### Feature request description Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL. ![image](https://user-images.githubusercontent.com/94965293/143841769-5fb4e571-1ae…

manuelgutierrezsigasi updated 5 months ago
1
EPFL-LAP/dynamatic #119

[scf] memory out-of-bound error

Benchmark: `symm_float.c` Script: ``` set-dynamatic-path ./dynamatic; set-src ./dynamatic/integration-test/symm_float/symm_float.c; set-clock-period 5; compile ; write-hdl --hdl veril…

Jiahui17 updated 1 month ago
1
rizonesoft/Notepad3 #4108

Support syntax highlighting for Verilog HDL

It is an enhancement request. VHDL is supported, but Verilog HDL is not.

mw-ypeng updated 1 year ago
2
YosysHQ/picorv32 #259

Verilog HDL Module Instantiation error at hx8kdemo.v(65)

Hi there, Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite. I have no problem synthesizing with [synth_area_top.v](https://github.com/YosysHQ/picorv32/blo…

YapWC updated 6 months ago
1
VSpaceCode/VSpaceCode #273

Support for HDLs like VHDL, Verilog & SystemVerilog?

## Problem There is no Major for any HDL(Hardware Description Language)s as I see it. Like VHDL, Verilog and SystemVerilog. ## Solution Implement Major modes for HDLs? ## Alternatives Develo…

sibeov updated 2 years ago
2
vitalets/github-trending-repos #50

New daily trending repos in Verilog

Subscribe to this issue and stay notified about new [daily trending repos in Verilog](https://github.com/trending/verilog?since=daily)!

vitalets updated 12 hours ago
12
efabless/openlane2 #543

Inject custom Verilog into the flow

### Description Hello! While writing a custom step I'm facing the challenge to inject custom Verilog into the flow. By this I mean the ability to add new files to the `VERILOG_FILES` variable. Unf…

mole99 updated 2 months ago
2
cocotb/cocotb #4164

Python Runner with Xcelium sets value for all parameters in …

Cocotb 1.9.1. I'm trying to set up a Verilog parameters in a testbench using Python runner. When using Python runner with Xcelium, it uses -gpg "object_name => value", which according to the …

Ustin updated 1 month ago
2

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