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There is a Platform config Makefile for Xilinx xrt named platforms.mk, but not for Altera opae. When I try to run opae synthesis in DevCloud, it gives missing DPLATFORM_MEMORY_BANKS, DPLATFORM_MEMORY_…
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I want to program the PL part of ZYNQ, but I need a backup of the bitstream. Where can I get it from? If you think about it, LibreSDR is a clone of PlutoSDR, but does that mean that a project for Viva…
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Currently, if you try to use a flip flop with a shaped input, the conversion fails when using `XilinxPlatform`.
Other places in the code might be affected to, I haven't checked that.
To reproduce:…
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For the fifo definition hazard3_frontend.v uses the same signals in a synchronous process (e.g. in fifo_update for `fifo_mem[0..FIFO_DEPTH-1]`) and an asynchronous process (e.g. boundary_conditions fo…
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It is an enhancement request.
VHDL is supported, but Verilog HDL is not.
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#### Feature request description
Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL.
s as I see it.
Like VHDL, Verilog and SystemVerilog.
## Solution
Implement Major modes for HDLs?
## Alternatives
Develo…
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Hi there,
Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite.
I have no problem synthesizing with [synth_area_top.v](https://github.com/YosysHQ/picorv32/blo…
YapWC updated
6 months ago
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Good evening,
I am trying to run the simulation file located in src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala using the commands exactly as they are inside the file. The simulation sta…