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When using the VHDL standalone formatter, "else" and "elsif" statements are indented one step too far to the right:
> command-line-1(("--eva…
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**Environment**
VSG 3.26.0
Windows 11
TerosHDL v6.0.10 (with VSG selected as VHDL formatter)
**Describe the bug**
When trying to Configuring Uppercase and Lowercase Rules the regex option appea…
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Just to get a final word on the format standards of the examples.
/cc @umarcor
- All files end with an empty line.
- No trailing white spaces at the end of lines.
- Tabs (not spaces) size 4. …
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When using the standalone VHDL formatter, if the indentation value is changed from empty to e.g 4 (the same way the other indentation settings work), when formatting the document 4 is printed on each …
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I have my first look on the clash compiler and about the readibility of the vhdl i'm raising some issues. I would like to know whether these issue are:
1. a shared concern for other developers
2. whet…
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**What is your question?**
DISCLAIMER: This is a question and suggestion. let me know if you want me to seperate the suggestion into a seperate issue for tracking my feature request.
I actively us…
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Formatter using VSG does not enforce prefix and suffix rules :
**To Reproduce**
rule file contains :
```
rule:
constant_015:
disable: false
prefixes: ['CST_']
```
vhdl fil…
knyfi updated
2 months ago