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I want the Makefile to support env vars to build specific versions of the tools in the toolchain.
For example, YOSYS_VERSION for Yosys.
It would then do git checkout $YOSYS_VERSION
It could be …
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## Steps to reproduce the issue
```
git clone https://github.com/adumont/hrm-cpu.git
cd hrm-cpu
git checkout issueABC
cd verilog
make bin
```
Failing commit is 2b4180c2bf508fead7d1d14def8600…
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With 0931ccc91985a725d305a5ca5ccc64f501745cdd it appears as though it's no longer possible to modify the Yosys template:
```sh
$ python .\foboot-bitstream.py --revision pvt --document-only --with…
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When migrating from arachne-pnr to nextpnr, loading a netlist that was converted to JSON, a segfault is triggered at line 624 of `jsonparse.cc` :
```C++
if (GetSize(pdir_node->data_dict_keys) != G…
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Hi,
I am trying to run the example in [Alhambra board](https://github.com/FPGAwars/Alhambra-II-FPGA), that contains a 12MHz clock and a iCE40HX4K fpga. I have managed to synthesize and upload the e…
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Consider the following trivial ice40 design (main.vl):
module main(// Leds, labeled D2 - D9 on the board.
output [9:2] d);
assign d[2] = 1;
assign d[3] = 0;
…
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I followed the dirrections here to try and program a TinyFPGA BX that I just got and when I get to the upload step it errors with `Error: the JSON object must be str, not 'bytes'`. I guess this is som…
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fedora 30 /usr/local/src for default directory
yosys, arachne-pnr, icestorm from repositories
yosys -V
Yosys 0.8 (git sha1 UNKNOWN, gcc 9.0.1 -O2 -fexceptions -fstack-protector-s…
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Do we require a testbench for the spi_hw? I tried the code with the same ice40 ultraplus board of lattice semiconductor, but my spi was not successful, just wanted to find where I am missing out. Kind…
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Hi,
is there a docker image, which contains the tools for the whole design flow (ghdl, ghdlsynth, yosys, nextpnr and icestorm)? I could only find images containing single tools.