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When running `python3 -m litex_boards.targets.digilent_arty --cpu-type femtorv --cpu-variant gracilis --variant a7-100 --toolchain vivado --load --build`
Meson is passed these settings:
`meson /…
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I've been experimenting with building the some of the risc-v targets, primarily on `boards/risc-v/litex/arty-a7` and `boards/risc-v/qemu-rv` with newer versions of the [riscv-gnu-toolchain](https://gi…
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I'm following this guide: https://github.com/enjoy-digital/litex/wiki/Use-GDB-with-VexRiscv-CPU
However, after starting litex_server and OpenOCD (`litex_server --uart --uart-port=/dev/ttyACM0 --bin…
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Hey, I want to build litex project with ethernet peripheral. I succesfully builded project and generated bit file. I'm trying to loading boot.json file but I got this error.
![image](https://github.…
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Hi,
I am trying to use the SCR1 SDK on **_Arty A7-100T_** board and was following the instructions given by **_arty_scr1_guide_en.pdf_**.
I can flash the memory with the part **_S25FL127S_** (refe…
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Try to flash the TE0711 Model, which is Using Xilinx Arty xc7a100tcsg324 chip, with S25FL256S QSPI chip. Checked the constrain files, they are using same as the /usr/local/share/openFPGALoader/spiOver…
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Hello,
Chipyard support rocket with NVDLA, but this project only support VCU118. I want to implement this rocket with NVDLA project on other FPGA prototyping paltform. Which means I can't use Xilinx …
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Since building the bitstreams takes quite some time but the resulting files are fairly small it would be nice to cache them.
Maybe even the additional build files like logs?
This would help a lot …
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Hi Olof,
I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires driven?
Thanks in advanc…
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Hi,
I have been trying to package up SymbiFlow for Gentoo in my [Portage overlay for FPGAs](https://github.com/StephanvanSchaik/fpga-overlay), but I am still running into issues with certain parts …