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Axi_stream.py is missing 'tid' and 'tdest' signal as per the standard AMBA 4 AXI4-Stream Protocol.
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
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after set(DATA_WIDTH 8 CACHE STRING "Data width"),When I make the shell, the HLS integration of the network stack will report an error. The error message is as follows:
(1)ERROR: [HLS 200-70] Compi…
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Replace duplicate IP from the Vitis Accelerated Libraries with the standard AXI4-Stream broadcast from the Vivado catalog.
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cocotbext-axi==0.1.16
Hello,
I am trying to drive my AXI4-Lite slave with this master:
self.axi_drv = AxiLiteMaster(AxiLiteBus.from_prefix(self.dut, "AXI4_LITE_"), self.dut.i_clk, self.dut.i_rs…
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I'm currently trying to simulate a VHDL project with nvc.
The project is included at https://github.com/ikwzm/PipeWorkTest.
You can download it as follows:
```console
shell$ git clone --branch…
ikwzm updated
2 years ago
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There are functions that should called only from a master, such as the toAxi4ReadOnly for Axi4 and m2sPipe for Stream.
How about add a check just like assert(this.isMaster) to those method.
or expli…
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I have implemented a block design with the packaged IP. I had a few doubts:-
1. How did you calculate the different parameters you have mentioned in your README.md such as SLICES, no:of registers, …
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I have successfully tested Axi4Downsizer without pipelining its inputs.
However, when I have implemented S2M pipelining for the input Axi4 writeData channel.
Because the valid signal of this channel…
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Has there been any consideration given to making the tproc64x32 IP have a configurable number of output channels instead of fixed at eight, so that the number can be set in Vivado? The reason I ask i…